Hyongsok T. Soh

Synthesis of individual single-walled carbon nanotubes on patterned silicon wafers

Recent progress in the synthesis of high-quality single-walled carbon nanotubes (SWNTs) has enabled the measurement of their physical and materials properties. The idea that nanotubes might be integrated with conventional microstructures to obtain new types of nanoscale devices, however, requires an ability to synthesize, isolate, manipulate and connect individual nanotubes. Here we describe a strategy for making high-quality individual SWNTs on silicon wafers patterned with micrometre-scale islands of catalytic material. We synthesize SWNTs by chemical vapour deposition of methane on the patterned substrates. Many of the synthesized nanotubes are perfect, individual SWNTs with diameters of 1–3 nm and lengths of up to tens of micrometres. The nanotubes are rooted in the islands, and are easily located, characterized and manipulated with the scanning electron microscope and atomic force microscope. Some of the SWNTs bridge two metallic islands, offering the prospect of using this approach to develop ultrafine electrical interconnects and other devices.

Integrated nanotube circuits: Controlled growth and ohmic contacting of single-walled carbon nanotubes

Single-walled carbon nanotubes are synthesized by chemical vapor deposition of methane at controlled locations on a substrate using patterned catalytic islands. The combined synthesis and microfabrication technique presented here allows a large number of ohmically contacted nanotube devices with controllable length to be placed on a single substrate. Transport studies demonstrate ohmic contacting, giving two-terminal resistances as low as 20 kΩ at low temperatures.

Fabrication of 0.1 μm metal oxide semiconductor field‐effect transistors with the atomic force microscope

Using the atomic force microscope (AFM), we have fabricated a metal oxide semiconductor field‐effect transistor (MOSFET) on silicon with an effective channel length of 0.1 μm. The lithography at the gate level was performed with the scanning tip of the AFM. The gate was defined by electric‐field‐enhanced selective oxidation of the amorphous silicon gate electrode. The electrical characteristics were reasonable with a transconductance of 279 mS/mm and a threshold voltage of 0.55 V.

Silicon micromachined ultrasonic immersion transducers

Broadband transmission of ultrasound in water using capacitive, micromachined transducers is reported. Transmission experiments using the same pair of devices at 4, 6, and 8 MHz with a signal‐to‐noise ratio greater than 48 dB are presented. Transmission is observed from 1 to 20 MHz. Better receiving electronics are necessary to demonstrate operation beyond this range. Furthermore, the same pair of transducers is operated at resonance to demonstrate ultrasound transmission in air at 6 MHz. The versatile transducers are made using silicon surface micromachining techniques. Computer simulations confirm the experimental results and are used to show that this technology promises to yield immersion transducers that are competitive with piezoelectric devices in terms of performance, enabling systems with 130 dB dynamic range. The advantage of the micromachined transducers is that they can be operated in high‐temperature environments and that arrays can be fabricated at lower cost.

Atomic force microscope lithography using amorphous silicon as a resist and advances in parallel operation

Lithography on (100) single‐crystal silicon and amorphous silicon is performed by electric‐field‐enhanced local oxidation of silicon using an atomic force microscope (AFM). Amorphous silicon is used as a negative resist to pattern silicon oxide, silicon nitride, and selected metals. Amorphous silicon is used in conjunction with chromium to create a robust etch mask, and with titanium to create a positive AFM resist. All lithographies presented here were patterned in parallel by arrays of two piezoresistive silicon or two silicon‐nitride cantilevers. Parallel arrays of five piezoresistive cantilevers were fabricated and used in imaging and lithographic applications. A 400 μm×100 μm parallel image is obtained in the time it would normally take to obtain a 100 μm×100 μm image. In our method of parallel operation, it is only possible to image and lithograph in modes that do not require feedback. In imaging, this limits the possible applications of the parallel AFM. During parallel lithography, discrepancies a...

NANOMETER SCALE LITHOGRAPHY AT HIGH SCANNING SPEEDS WITH THE ATOMIC FORCE MICROSCOPE USING SPIN ON GLASS

We have identified a resist material that is suitable for high‐speed, nanometer‐scale scanning probe lithography (SPL) using the atomic force microscope (AFM). The material is siloxene, commonly known as spin on glass (SOG). The SOG film is deposited on a silicon sample and exposed with a voltage applied between the AFM tip (negative) and the silicon substrate (positive). Voltages of 70 V and currents of 1 nA are typical. It is a positive resist where the etch selectivity between the exposed and unexposed areas is greater than 20. We have recorded line widths as narrow as 40 nm. The writing speed is greater than 1 mm/s, which we believe to be an important attribute in future systems for SPL.

Nanometer-scale patterning and individual current-controlled lithography using multiple scanning probes

Scanning probe lithography (SPL) is capable of sub-30-nm-patterning resolution and nanometer-scale alignment registration, suggesting it might provide a solution to the semiconductor industry’s lithography challenges. However, SPL throughput is significantly lower than conventional lithography techniques. Low throughput most limits the widespread use of SPL for high resolution patterning applications. This article addresses the speed constraints for reliable patterning of organic resists. Electrons field emitted from a sharp probe tip are used to expose the resist. Finite tip-sample capacitance limits the bandwidth of current-controlled lithography in which the tip-sample voltage bias is varied to maintain a fixed emission current during exposure. We have introduced a capacitance compensation scheme to ensure continuous resist exposure of SAL601 polymer resist at scan speeds up to 1 mm/s. We also demonstrate parallel resist exposure with two tips, where the emission current from each tip is individually c...

Resist Exposure Using Field-Emitted Electrons

Early scanning probe lithography (SPL) studies were limited to demonstrations of the technique’s fine resolution. A few groups fabricated devices using SPL [1][2][3], but such work was directed toward creating a single working device suitable for research or exploration. Methods used by these groups suffer from speed constraints and poor repeatability, thus it is unlikely they can be easily extended to large-scale fabrication applications. We sought to develop a method of SPL suited to semiconductor lithography, where accuracy, reliability, and throughput are essential.

High Speed Resist Exposure With a Single Tip

We have shown that current-controlled scanning probe lithography (SPL) can reliably pattern nanometer-scale features in resist. However, the serial nature of SPL makes it much slower than mask-based techniques such as photolithography, x-ray lithography, or extreme ultraviolet lithography. An advantage of a direct write approach is that it does not require expensive and time-consuming mask fabrication. SPL may also have superior alignment capabilities. Nevertheless, in order for SPL to become a viable technology for high-resolution semiconductor lithography, the throughput must be dramatically increased.

Critical Dimension Patterning Using SPL

Transistor gate patterning is the primary application of a high-resolution lithographic system in the semiconductor industry. The gate itself is typically a long, narrow line of polysilicon whose width (known as the transistor gate “length”) determines the device switching speed. The uniformity of the gate is critical for device electrical performance and yield. Gate patterning is performed after significant device processing. Therefore the feature must be accurately aligned to the previously patterned regions. It must also be written over the sample topography created by the prior fabrication steps.