Kathryn Wilder Guarini

Scanning probe lithography

List of Figures. List of Tables. Glossary. Foreword. Preface. Acknowledgments. 1. Introduction to Scanning Probe Lithography. 2. SPL by Electric-Field-Enhanced Oxidation. 3. Resist Exposure Using Field-Emitted Electrons. 4. SPL Linewidth Control. 5. Critical Dimension Patterning Using SPL. 6. High Speed Resist Exposure With a Single Tip. 7. On-Chip Lithography Control. 8. Scanning Probe Tips for SPL. 9. Scanning Probe Arrays for Lithography. Epilog. List of Publications. Index.

Microfabricated silicon solid immersion lens

We present the microfabrication of a solid immersion lens from silicon for scanning near-field optical microscopy. The solid immersion lens (SIL) achieves spatial resolution better than the diffraction limit in air without the losses associated with tapered optical fibers. A 15-/spl mu/m-diameter SIL is formed by reflowing photoresist in acetone vapor and transferring the shape into single-crystal Si with reactive ion etching. The lens is integrated onto a cantilever for scanning, and a tip is fabricated opposite the lens to localize lens-sample contact. Using the Si SIL, we show that microfabricrated lenses have greater optical transparency and less aberration than conventional lenses by focusing a plane wave of 633-nm light to a spot close to a wavelength in diameter. Microlenses made from absorbing materials can be used when the lens thickness Is comparable to the penetration depth of the light. Tolerance to errors in curvature and thickness is improved in micromachined lenses, because spherical aberrations decrease with lens diameter. We demonstrate scanning near-field optical microscopy with the Si SIL and achieve spatial resolution below the diffraction limit in air by resolving 200-nm lines with 633-nm light.

Resist Exposure Using Field-Emitted Electrons

Early scanning probe lithography (SPL) studies were limited to demonstrations of the technique’s fine resolution. A few groups fabricated devices using SPL [1][2][3], but such work was directed toward creating a single working device suitable for research or exploration. Methods used by these groups suffer from speed constraints and poor repeatability, thus it is unlikely they can be easily extended to large-scale fabrication applications. We sought to develop a method of SPL suited to semiconductor lithography, where accuracy, reliability, and throughput are essential.

High Speed Resist Exposure With a Single Tip

We have shown that current-controlled scanning probe lithography (SPL) can reliably pattern nanometer-scale features in resist. However, the serial nature of SPL makes it much slower than mask-based techniques such as photolithography, x-ray lithography, or extreme ultraviolet lithography. An advantage of a direct write approach is that it does not require expensive and time-consuming mask fabrication. SPL may also have superior alignment capabilities. Nevertheless, in order for SPL to become a viable technology for high-resolution semiconductor lithography, the throughput must be dramatically increased.

Critical Dimension Patterning Using SPL

Transistor gate patterning is the primary application of a high-resolution lithographic system in the semiconductor industry. The gate itself is typically a long, narrow line of polysilicon whose width (known as the transistor gate “length”) determines the device switching speed. The uniformity of the gate is critical for device electrical performance and yield. Gate patterning is performed after significant device processing. Therefore the feature must be accurately aligned to the previously patterned regions. It must also be written over the sample topography created by the prior fabrication steps.

Scanning Probe Tips for SPL

This chapter presents the required features of probe tips for scanning probe lithography (SPL) and some novel methods for tip fabrication. For both field-induced oxidation and electron exposure SPL, probe tips must be electrically conductive and sharp to enable field concentration at the tip apex. For field emission of electrons from the tips, the workfunction of the tip material is significant. In the case of feedback control of the emitted current, the tips should be tall to ensure a small cantilever-to-sample capacitance. In this chapter we give details on different tip varieties: (1) “standard” silicon or metal-coated tips, (2) post-processed silicon tips, and (3) carbon nanotubes as scanning probe tips.

SPL Linewidth Control

The current-controlled scanning probe lithography (SPL) systems that we developed (described in Chapter 3) can reliably pattern uniform features in organic resists with dimensions below 100 nm. In this chapter, we compare electron exposures made by SPL to those made by electron beam lithography (EBL). This comparison highlights the advantages and limitations of a low-energy electron lithography technique such as SPL.

Introduction to Scanning Probe Lithography

Semiconductor lithography is the patterning process used to define the structures that make up integrated circuits (ICs). The semiconductor industry has historically scaled down the size of printed features on ICs because scaling both improves transistor performance and reduces the area that devices occupy. Today the patterning technology employed in manufacturing is photolithography, a process that uses ultraviolet light to define submicron-sized features in photosensitive polymers. Since photolithography is rapidly approaching fundamental resolution limitations, a new high-resolution patterning technique may be required to continue the industry’s trend toward higher performance electron devices, increased packing densities, and higher density memories.

SPL by Electric-Field- Enhanced Oxidation

SPL by electric-field-enhanced oxidation was introduced by Dagata [5] in his pioneering study of patterning hydrogen passivated single crystal silicon with the scanning tunneling microscope (STM). The lithography begins by removing the native oxide and hydrogen passivating the silicon surface in hydroflouric acid (HF). Then the tip of a scanning probe with a voltage bias (typically a few volts) is brought to the vicinity of the surface creating an intense electric field. The magnitude of this electric field can be in excess of 1 V/nm. A schematic diagram of the experimental set up is shown in Fig. 2.1.

On-Chip Lithography Control

Our preferred method of scanning probe lithography (SPL) uses electrons field emitted from a micromachined probe tip in air to expose organic polymer resists. The pattern dimension is set by the electron exposure dose delivered to the resist. Control of the exposure dose has been achieved previously through external feedback circuitry. Typically the emission current is measured and compared with the desired (or setpoint) current. A signal is sent to adjust either the tip-sample voltage [1–3] or the tip-sample distance [4–6] in order to ensure that the measured current does not deviate significantly from the setpoint. In place of this feedback circuitry, we integrated a transistor current source onto the cantilever chip to control the electron exposure dose delivered to the resist. In this chapter we describe the design, fabrication, and operation of this integrated current source.