Hyuk Su Son

A Reconfigurable Quad-Band CMOS Class E Power Amplifier for Mobile and Wireless Applications

This paper proposes a new design technique for a reconfigurable CMOS Class E power amplifier (PA) by selectively activating the transistor cells in the array of power transistors. The activated transistors will be used for amplification and the non-activated transistors will be used for input/output matching and switching capacitance for Class E operation. The quad-band PA for 1.9/2.3/2.6/3.5 GHz has been implemented in a 0.18 μm CMOS technology using the technique without any switch or tunable circuit. This PA obtains output powers of 24.2/23.8/23.4/ 20.5 dBm and efficiency of 48.2/44.3/40.9/35.6% at 1.9/2.3/2.6/ 3.5 GHz. The total MMIC chip size is as small as 0.92 × 1.75 mm2 for the reconfigurable quad-band operation.

An efficient voltage-mode class-D power amplifier for digital transmitters with delta-sigma modulation

A high efficiency voltage-mode class-D power amplifier for digital transmitters with delta-sigma modulation is demonstrated using a 0.13-µm 1.2-V silicon-on-insulator (SOI) CMOS technology. To minimize the overlap of ON time of both the PMOS and the NMOS transistors, a shoot-through current reduction technique was employed. Distortion induced by parasitic inductance was mitigated with integrated on-chip capacitors. The amplifier was tested with periodic signals, envelope delta-sigma modulation (EDSM) signals, and band-pass delta-sigma modulation (BPDSM) signals at 800MHz. Peak drain efficiencies of 75, 62, and 55% were obtained for these inputs, together with ACPR of −60dBc for EDSM EDGE signals and −43dBc for BPDSM CDMA signals.

A CMOS Envelope-Tracking Transmitter With an On-Chip Common-Gate Voltage Modulation Linearizer

This letter presents a fully integrated CMOS envelope-tracking transmitter with an on-chip common-gate voltage modulation linearizer that achieves an average output power of 26/23.5 dBm with a PAE of 33/28%, an ACLR of -33 / -32.5 dBc at a frequency of 1.9 GHz for 3.84 MHz BW 3.5 dB PAPR WCDMA and 5 MHz BW 7.5 dB PAPR LTE signals in an 0.18-μm CMOS process. The CMOS ET transmitter is integrated with an envelope amplifier, two pairs of saturated power amplifiers, and an on-chip linearizer. The total chip size is 2.5 × 1.5 mm2 with the input/output on-chip transformers and matching networks.

Single-Ended CMOS Doherty Power Amplifier Using Current Boosting Technique

In this letter, an efficiency enhancement technique incorporating a gate-voltage boosting of a peaking power amplifier (PA) in a CMOS Doherty PA is presented. To compensate the current driving capability from the low dc bias point of the peaking cell, an auxiliary bias network consisting of an operational amplifier (OPA) is utilized to provide the corresponding gate voltage in accordance with an instantaneous output power level. To verify the superior performance of the proposed technique, a CMOS Doherty PA with a prototype OPA has been fabricated using a commercial 0.18 μm process. The experimental results show that the implemented PA has an overall efficiency of 43.6% and a gain of 27.2 dB at an average output power of 25.2 dBm for a 10 MHz 3G LTE signal with a 7.6 dB peak-to-average power ratio (PAPR). Under this situation, the spectral performance is -34.1 dBc.

Envelope Amplifier With Multiple-Linear Regulator for Envelope Tracking Power Amplifier

In this paper, a new envelope amplifier (EA) scheme incorporating a linear regulator array is presented. The proposed EA achieves a higher efficiency over a wide envelope range utilizing multiple linear regulators. The linear regulators biased as multiple supply voltages are responsible for delivering a partial envelope current, ensuring high efficiency. A simulation revealed the superior performance efficiency of the proposed scheme in terms of the instantaneous envelope voltage compared with that of a conventional EA. Based on the simulation results, an envelope tracking (ET) amplifier consisting of the proposed EA was implemented using a commercially available 60-W gallium-nitride (GaN) device. The experimental results show that the implemented ET system has an overall efficiency of 47.8% and a gain of 14 dB at an average output power of 40.8 dBm. In this situation, the spectral performance is less than -49.5 dBc using the optimum digital predisotortion functionality.

A fully integrated triple-band CMOS hybrid-EER transmitter for WCDMA/LTE applications

This paper presents a fully integrated triple-band CMOS hybrid-EER transmitter for WCDMA/LTE applications. The operation frequency bands are 0.8/2.3 GHz for LTE and 1.9 GHz for WCDMA applications with multi-band class-E power amplifier (PA) using a power cell resizing technique and a multitap transformer. The multi-mode envelope amplifier support 3.84-MHz WCDMA and 5-MHz LTE signal with a dual-switching stage for high efficiency. The PA and envelope amplifier are integrated in a single chip using CMOS process with input/output matching networks. To compensate the nonlinearity of the supply modulated transmitter, the on-chip linearizer is design on a chip. The transmitter achieves output powers of 23/26/22 dBm and power-added efficiency of 27/33/23 % at each frequency band. The transmitter is implemented in a 0.18 μm CMOS process. The total chip size is 1.6 × 2.5 mm2.

A triple-band CMOS class-E power amplifier for WCDMA/LTE applications

This paper presents a fully integrated triple-band CMOS class-E power amplifier (PA) for WCDMA (1.9 GHz) and LTE (1.8 GHz and 2.6 GHz) applications. The triple-band operation is achieved by activating selectively transistor cells and matching the transistor cells with low/high-band on-chip transformers for the three different frequencies. The PA is fabricated using a 0.18-μm CMOS process and has a chip size of 1.5 × 1.85 mm2 including matching networks and transformers. This PA obtains output powers of 27.8/28.1/27.4 dBm at 1.8/1.9/2.6 GHz in continuous wave (CW) modes, respectively. The PA implemented to hybrid-EER structure satisfied the ACLR requirements up to 21 dBm for WCDMA (1.9 GHz) and up to 18 dBm and 16.3 dBm for LTE (1.8 GHz and 2.6 GHz) without any linearization technique.

A Fully Integrated Triple-Band CMOS Class-E Power Amplifier With a Power Cell Resizing Technique and a Multi-Tap Transformer

This letter presents a fully integrated triple-band CMOS class-E power amplifier (PA) for the 0.8/1.9/2.4 GHz frequencies. The operating frequency band is tuned by a power cell resizing technique and by changing the supply bias position with a multi-tap transformer for the required capacitance and inductance values for optimum class-E operation. The PA achieves output powers of 28/29.6/26.5 dBm and power-added efficiency of 40/45/37% at each frequency band. The PA is implemented in a 0.18 μm CMOS process without multiple transformers or input/output matching networks. The total chip size is 1.5 × 1.5 mm2.

A Fully Integrated CMOS Class-E Power Amplifier for Reconfigurable Transmitters with WCDMA/WiMAX Applications

This paper presents a dual-band CMOS power amplifier (PA) using class-E topology for Wideband Code Division Multiple Access (WCDMA) at 1.9 GHz and Worldwide Interoperability for Microwave Access (WiMAX) at 2.6 GHz applications. The fully integrated PA consists of an input balun, a driver stage, a power stage, and two output transformers. To operate the dual-band PA, common-gate amplifiers having on-off apparatuses in power stage and matched transformers for 1.9/2.6 GHz are employed. The PA is designed and fabricated in a 0.18-μm CMOS technology and has a chip size of 1.5 × 1.85 mm2 including all pads. When driven by continuous wave (CW) signals, the output power and the efficiency reach 28.1/27.4 dBm and 37.8/31.6% at 1.9 GHz and 2.6 GHz, respectively. The average output powers of the hybrid-EER based TX system 21 dBm for 3.84 MHz WCDMA and 12 dBm for 5 MHz WiMAX, while also meeting stringent linearity specifications without using any linearization methods.

A hybrid envelope amplifier with switching-controlled structure for EDGE/WCDMA/LTE reconfigurable transmitters

This paper presents a new type of the hybrid envelope amplifier (HEA) using a switching-controlled structure for reconfigurable transmitters. The dual switching stage, controlled by an appropriate voltage with respects to the selected mode, is employed to obtain high efficiency. For verification, the proposed HEA has been fabricated using 0.35-µm CMOS technology within an area of 2.3 × 1.1 mm2 including all of the pads. The maximum efficiency of 85%, 84% and 79%, which are approximately 9%, 6% and 5% higher than those of the conventional HEA, are achieved for EDGE, WCDMA, and LTE modes, respectively.