Chae Jun Lee

A Wideband Aperture Efficient 60-GHz Series-Fed E-Shaped Patch Antenna Array With Copolarized Parasitic Patches

A novel series-fed E-shaped patch antenna array with copolarized parasitic patches for enhanced aperture efficiency at 60-GHz unlicensed wideband applications is proposed. The additional radiation from the inserted copolarized parasitic patches between series-fed patches improves the gain flatness remarkably as well as the gain and aperture efficiency, because of the offset resonant frequency. The four-array antenna with parasitic patches presents 0.8-dB gain flatness over the whole 57-66 GHz unlicensed band, 14.5 dBi peak gain, and 63.6% aperture efficiency while that without parasitic patches shows 1.4-dB flatness, 13.4 dBi peak gain, and 49.2% aperture efficiency, without any change in the antenna size,

A D-Band Gain-Boosted Current Bleeding Down-Conversion Mixer in 65 nm CMOS for Chip-to-Chip Communication

6.0\times 14.7\times 0.25

An 20-Gb/s W-Band OOK CMOS Receiver for High-Speed Wireless Interconnect

mm2.

Low power and high speed OOK modulator for wireless inter-chip communications

A D-band gain-boosted current-bleeding down-conversion mixer is presented in this letter using 65 nm CMOS technology. The proposed downconversion mixer uses a gain-boosted current-bleeding technique to improve the conversion gain for low power chip to chip communication with a low local oscillator (LO) power. Broadband Marchand baluns were used to transform a single-ended signal to a differential signal at the RF and LO port for measurement. According to experimental results, the proposed mixer had a measured conversion gain of -12 ± 1 dB at a frequency range from 113 to 127 GHz with an ultra-low LO power of -9 dBm using a gain-boosted current bleeding technique. The LO-to-RF isolation was better than -30 dB. This core chip occupies 350 × 320 μm2. The power consumption is 6 mW from a 1 V supply voltage.

Low-profile wideband E-shaped patch antenna for 60GHz Communication

This letter presents a high-speed and low-power consuming on-off keying (OOK) receiver implemented on 65-nm Si-CMOS process. The receiver uses OOK modulation for the low-power consumption and operates at a high-data rate due to wide-bandwidth circuitry. The receiver consists of a wideband low-noise amplifier (LNA), a gain-boosting detector and a third-order active feedback amplifier. The receiver consumes 46 mW at 1 V supply and occupies 0.64 mm2 including all pads. The receiver achieves 20 Gb/s at a bit-error rate (BER) less than 10-11 for 27-1 pseudorandom binary sequence (PRBS). The sensitivity is -29 dBm at 20 Gb/s data rate, and the energy per bit exhibits 2.3 pJ/bit. To the best of our knowledge, this receiver achieves the highest data rate at the single carrier modulation and the lowest energy per bit among the previously published millimeter-wave Si-CMOS OOK receivers.

A W-band CMOS low power wideband low noise amplifier with 22 dB gain and 3dB bandwidth of 20 GHz

Millimeter-wave on-off keying (OOK) modulator for wireless inter-chip communications is proposed. The proposed modulator not only has a wide bandwidth which allows the high speed modulation but also operates with a low power consumption enhancing the power efficiency and assures the inter-chip communication. With wide bandwidth and the OOK modulation scheme, it can process data having 12 Gbps while consuming a little DC power showing the energy efficiency of 0.75 pJ/bit. The on/off ratio of the circuit is higher than 25 dB assuring little degradation on the SNR. The chip size using 65 nm GP RF CMOS is 0.254 mm2 which is very compact compared to other state-of-the-art works.

A 60 GHz LTCC antenna in package with low power CMOS radio

This paper presents a low profile, wideband E-shaped patch antenna for a 60 GHz communication system. Two slots are placed into the antenna to provide wide-band characteristics. The proposed antenna can provide a peak gain of 9.2 dBi with 22.5% of 3-dB gain bandwidth and 22% of wide impedance bandwidth. The simulated and measured radiation pattern is also presented.

A 117 GHz all-parallel sub-harmonically Injection-Locked quadrature CMOS voltage-controlled oscillator

This paper presents a W-band low power, wideband low noise amplifier design in 65nm CMOS. Low noise amplifier consists of six-stage to obtain high gain. For a high-data rate communication system, the wideband characteristic is very important. In order to enhance the 3 dB bandwidth, a two-center frequency technique is used. In addition, the amplifier was realized by a conjugate matching technique to achieve low-loss between each stage. The measured results show that the LNA can provide a gain of 22dB with a 3 dB bandwidth of 20 GHz. The LNA consumes 21 mW from a 1 V supply voltage, achieving S11 better than -10 dB for frequencies 67~ over 110 GHz, S22 better than -10 dB for frequencies 69~102 GHz. Furthermore, the LNA achieves minimum noise figure (NF) of 6.8 dB at 81 GHz and NF of 6.8~10.4 dB within a 3 dB gain bandwidth.

120GHz low power, high gain, wideband active balun for chip-to-chip communication

A 60 GHz LTCC Antenna in Package with low power CMOS Radio solution for high data-rate and short-range wireless mobile communication are presented in this paper. For low power consumption, a new type of OOK system is proposed. The 60 GHz OOK transmitter and receiver are designed in 90 nm CMOS process. The transmitter with an OOK modulator and a VCO added an output buffer consumes 27.32 mW power and is able to modulate over 2 Gbps. The receiver with a LNA, a demodulator and a baseband amplifier consumes 12.92 mW and has ability to recover up to 5 Gbps. The OOK system is integrated with low loss compact LTCC AiP. The low loss AiP techniques mainly consist of inter-connection and antenna design methods. The direct wire bonding inter-connection with matched elements has under 1 dB insertion loss. The 60 GHz micro-strip patch antenna has over 90 percent efficiency with LTCC substrate. In the end, high data rate video demonstration using the low power wireless system are presented.

High-speed and low-power OOK CMOS transmitter and receiver for wireless chip-to-chip communication

Injection-Locked quadrature voltage-controlled oscillator (QILO) is designed in this paper at 117GHz frequency. To get good low-phase performance, sub-harmonically injection locked structure is used. A 38.8 ~ 39.3GHz input signal is sub-harmonically injected in parallel to the tank and core quadrature VCO is designed as a parallel-coupled scheme. The chip is fabricated in a 65nm CMOS technology and shows a phase noise -100.9dBc/Hz at 1MHz offset, a tuning range of 116.7 ~ 117.7GHz, a locking range of 0.4GHz, a 50-ohm matched output power of -10 ~ -11dBm, and a simulated phase error of 1.7°.