Hyun-koo Kang

Double quadrature harmonic rejection architecture insensitive to gain and phase mismatch for analog/digital TV tuner IC

Image rejection and harmonic rejection are important performance parameters in wideband low-IF TV system. In this paper, double quadrature harmonic rejection architecture insensitive to gain and/or phase mismatch is proposed to satisfy stringent image rejection ratio (IRR) and harmonic rejection ratio (HRR) for analog/digital TV tuner ICs. Fabricated in 0.13µm CMOS process, more than 60dB of the IRR is achieved over 42–864MHz RF frequency and more than 69dB of the 3rd HRR is achieved over 42–306MHz RF frequency without any calibration.

A research on power complementary bipolar technology to prevent parasitic operation

A 2 /spl mu/m design ruled, High-Densified, and Low-Power-Consuming Bipolar Integrated Circuit process has been developed. The breakdown voltage of the transistor is 15 V and it has a stable current driving capability at high current (about 1 A) due to the low saturation voltage between emitter and collector. NPN Tr. has been fabricated to prevent leakage current and has good Cut-Off frequency (fT=5 GHz) by using a polysilicon emitter. The characteristics of this process is a Double Epi Process to form a high concentrated N+BL in VPNP Tr. (that is the same as in NPN Tr.) which can protect the parasitic Tr. operation like Latch-Up Phenomenon (Ihold=26 mA, Pa-PNP Tr, hFE=4). And it also includes the IIL Device without an additional mask layer. This process is a low voltage, high current power complementary bipolar process that merges a variety of NPN, VPNP, LPNP, SPNP, IIL devices, and a diffusion resistor.