Jae-Young Ryu

A 128-ch Δ-Σ ADC based mixed signal IC for full digital beamforming Wireless handheld Ultrasound imaging system.

This paper reports a massively integrated Δ-Σ ADC based mixed signal chipset for a handheld Wireless Ultrasound imaging system. The IC has been fabricated in a standard 0.13 μm 1.5V 7M2F CMOS process with 128 parallel channels containing Delta-Sigma (Δ-Σ) ADCs, Anti-aliasing filter, Decimation filters, Serializers and LVDS drivers. The entire chip is SPI controlled and allows group-level power control through an FPGA. The IC measures 15 × 15 mm and dissipates around ~ 4.6 W of power, with 12-bit resolution at 20 Msps sample rate. The chip was packaged in a thermally stable BGA package and demonstrated in a handheld ultrasound battery operated system with complete digital beamforming.

Double quadrature harmonic rejection architecture insensitive to gain and phase mismatch for analog/digital TV tuner IC

Image rejection and harmonic rejection are important performance parameters in wideband low-IF TV system. In this paper, double quadrature harmonic rejection architecture insensitive to gain and/or phase mismatch is proposed to satisfy stringent image rejection ratio (IRR) and harmonic rejection ratio (HRR) for analog/digital TV tuner ICs. Fabricated in 0.13µm CMOS process, more than 60dB of the IRR is achieved over 42–864MHz RF frequency and more than 69dB of the 3rd HRR is achieved over 42–306MHz RF frequency without any calibration.