Hyun-Kyu Jeon

An Intra-Panel Interface With Clock-Embedded Differential Signaling for TFT-LCD Systems

In this paper, an intra-panel interface with a clock embedded differential signaling for TFT-LCD systems is proposed. The proposed interface reduces the number of signal lines between the timing controller and the column drivers in a TFT-LCD panel by adopting the embedded clock scheme. The protocol of the proposed interface provides a delay-locked loop (DLL)-based clock recovery scheme for the receiver. The timing controller and the column driver integrated with the proposed interface are fabricated in 0.13- μm CMOS process technology and 0.18-μm high voltage CMOS process technology, respectively. The proposed interface is verified on a 47-inch Full High-Definition (FHD) (1920RGB×1080) TFT-LCD panel with 8-bit RGB and 120-Hz driving technology. The maximum data rate per differential pair was measured to be as high as 2.0 Gb/s in a wafer test.

Semi-recursive VLSI architecture for two dimensional discrete wavelet transform

This paper presents an efficient two-dimensional discrete wavelet transform (2-D DWT) VLSI architecture which calculates the 2-D DWT for image processing in real-time. The proposed architecture, semi-recursive 2-D DWT VLSI architecture, has the minimum H/W cost of internal word length, data-bus utilization, scheduling control overhead and storage size. Compared with the conventional recursive 2-D DWT VLSI architecture, the size of multipliers and registers are reduced by 13% and 34% respectively. Furthermore, the semi-recursive 2-D DWT VLSI architecture exploits the lapped block processing and hence has the minimum transposition storage size and short latency.

64.5L: Late‐News Paper: A Clock Embedded Differential Signaling (CEDS™) for the Next Generation TFT‐LCD Applications

A CEDS™ (Clock Embedded Differential Signaling) interface for the next generation TFT-LCD applications is proposed. The proposed intra-panel interface reduces the number of signal lines in the TFT-LCD panel by embedding the clock signal in transmitted data without explicit clock lines, and it provides low EMI, low power consumption and high data rate. The CEDS protocol provides an embedded clock recovery scheme which is based on the delay-locked loop (DLL). The CEDS interface is verified on a 42-inch full-HD (1920×1080) TFT-LCD panel with the 10-bit RGB and 120Hz driving technology. The maximum data rate is measured as higher than 1.405Gb/s, with a pixel clock frequency of up to 330MHz.

6.4: A Clockembedded Voltage Differential Signaling CVDS for the ChipOnGlass Application of TFTLCD

An intrapanel interface for the ChipOnGlass COG application is developed using a Clockembedded Voltage Differential Signaling CVDS. The proposed interface adopts an embedded clock scheme to eliminate the skew between data and clock signals. The transmitter and receiver for the proposed interface are equipped with the transition compensator and equalizer to overcome the frequency limitation caused by highly resistive LineOnGlass LOG of the COG application. The maximum data rate per pair is measured as high as 780Mbps at the prototype with the refresh rate up to 105Hz. The proposed interface achieves low electromagnetic interference EMI and low power consumption. The power consumption of the proposed interface is reduced by 50% compared to the conventional interfaces for the COG application.

High speed serial interface for mobile LCD driver IC

A high speed serial interface is proposed for a mobile VGA-resolution TFT-LCD driver IC. This high speed serial interface is intended to replace the legacy RGB interface for the LCD driver ICs. The transmission channel consists of one clock and two data differential lines, and thereby we can reduce the number of signal lines going through the hinge of a mobile phone from 28 down to 6. The simple synchronization encoding scheme facilitates the pixel synchronization. All channels conform to sub low-voltage differential signaling (SubLVDS) convention. The total data transfer rate can be up to 800 Mbps for two data channels.

P‐243L: Late‐News Poster: A 480‐Output TFT‐LCD Source Driver IC for COG Applications

A 480-output TFT-LCD source driver IC for a COG (Chip On Glass) application is presented. To reduce the cost of the TFT-LCD module, COG technology is being adopted for the portable display devices. To achieve the high data rate transfer on the COG-type TFT-LCD module, an ACDS (Advanced Current-mode Differential Signaling) interface is proposed. The offset compensating algorithm is adopted to alleviate the block dim phenomenon due to the offset of internal gamma buffers. The driver IC was fabricated in 0.35um high voltage CMOS technology process and evaluated with 13.3-inch diagonal wide XGA (1280RGB×800) TFT-LCD module of which cost was reduced significantly.

An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface

This paper presents a reference-less digital clock and data recovery (CDR) for liquid crystal display (LCD) intra-panel interfaces. The increments of the display resolution, the color depth, and frame rate demand high speed transmission capacity between timing controller and source driver IC (SDIC). As the data rate increases, the performances of the CDR in the SDIC especially for the tolerance of input jitter and ground noise become important to recover the data without an error. This work exploits the half-bit previous input data with feed forward method and early/late signal from CDR to be tolerant to the input jitter and power noise. Two prototypes are tested with half-rate clocking at 5 Gb/s data rate, and quarter-late clocking at 10 Gb/s data rate. Both 5 Gb/s and 10 Gb/s prototypes improve the tolerance of the input jitter and power noise. Fabricated in 65 nm CMOS technology, the test chips consume 17.44 mW and 20.7 mW, respectively.

40.2: An Improved Differential Signaling Scheme for the Chip-On-Glass Application of TFT-LCD

An improved signaling scheme for the intra-panel interface for the chip-on-glass (COG) application is proposed. The proposed signaling scheme adopts a transmitter with the current-mode driver with shunt termination for an impedance matching on the transmitter and a receiver without termination to eliminate the multiple reflections on the transmitter. It obtains good signal quality on the receiver without additional current consumption. The transmitter for the proposed signaling scheme adopts the current-mode driver with shunt termination instead of the voltage-mode driver with series termination resistor for minimizing the effect caused by the process dependency of the circuitry in the transmitter. The receiver for the proposed signaling scheme is equipped with the loss compensator to equalize the channel loss caused by the highly resistive signal line-on-glass (LOG) and low channel bandwidth due to open termination on the receiver. The proposed signaling scheme is verified with 9.7-inch XGA (1024RGB×768) resolution TFT-LCD module for tablet computer. The proposed signaling scheme achieves the low electromagnetic near-field radiation from the signal lines by acquiring the good signal integrity on the transmission channel.

Design of a noise-free microcontroller

This paper described the new design technology for implementation of noise-free microcontroller unit (MCU), called Nfree/sup TM/ technology that is the solution proposed by Hyundai Electronics Co. Ltd. Preventing an erroneous operation due to noise is one of the basic requirements of many systems and is more seriously required by the MCU that controls the system. Also the power noise is one of the most serious noise sources that causes the MCU to malfunction. Therefore, we proposed the novel power noise preventing circuit scheme, called Nfree/sup TM/ technology. If the power falls below the voltage level of power failure, the MCU with Nfree/sup TM/ technology can be reset, frozen or stopped to preserve the system from the malfunction due to the power noise. In an MCU with Nfree/sup TM/ technology, the voltage level of power failure and the operating mode that resets, freezes or stops the MCU can be selected by software according to the applications.