Lee-Sup Kim

An advanced contrast enhancement using partially overlapped sub-block histogram equalization

In this paper, an advanced histogram equalization algorithm for contrast enhancement is presented. Histogram equalization is the most popular algorithm for contrast enhancement due to its effectiveness and simplicity. Global histogram equalization is simple and fast, but its contrast enhancement power is relatively low. Local histogram equalization, on the other hand, can enhance overall contrast more effectively, but the computational complexity is very high due to its fully overlapped sub-blocks. For high contrast and simple calculation, a low pass filter type mask is proposed. The low pass filter type mask is realized by partially overlapped sub-block histogram equalization (POSHE). With the proposed method, the computation overhead is reduced by a factor of about one hundred compared to that of local histogram equalization while still achieving high contrast.

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

The two-dimensional discrete cosine transform (2D DCT) has been widely recognized as a key processing unit for image data compression/decompression. In this paper, the implementation of a 200 MHz 13.3 mm/sup 2/ 8/spl times/8 2-D DCT macrocell capable of HDTV rates, based on a direct realization of the DCT, and using distributed arithmetic is presented. The macrocell, fabricated using 0.8 /spl mu/m base-rule CMOS technology and 0.5 /spl mu/m MOSFETs, performs the DCT processing with 1 sample-(pixel)-per-clock throughput. The fast speed and small area are achieved by a novel sense-amplifying pipeline flip-flop (SA-F/F) circuit technique in combination with nMOS differential logic. The SA-F/F, a class of delay flip-flops, can be used as a differential synchronous sense-amplifier, and can amplify dual-rail inputs with swings lower than 100 mV. A 1.6 ns 20 bit carry skip adder used in the DCT macrocell, which was designed by the same scheme, is also described. The adder is 50% faster and 30% smaller than a conventional CMOS carry look ahead adder, which reduces the macrocell size by 15% compared to a conventional CMOS implementation. >

A low-power SRAM using hierarchical bit line and local sense amplifiers

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V/sub DD//10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K/spl times/32 bits is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.

Winscale: an image-scaling algorithm using an area pixel model

We propose a new scaling algorithm, winscale, which performs the scale up/down transform using an area pixel model rather than a point pixel model. The proposed algorithm has low complexity: the algorithm uses a maximum of four pixels of an original image to calculate one pixel of a scaled image. Nevertheless, the algorithm has good characteristics such as fine-edge and changeable smoothness. We implemented a hardware design of winscale using an FPGA and displayed some test scenes in an liquid crystal display panel using a digital visual interface. The hardware cost and the image quality were compared with those of the conventional image scaling algorithms. It is proved that winscale has good scale property with low complexity. Winscale can be used in various digital display devices that need image scaling, especially in applications that require good image quality with low hardware cost.

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.

200 MHz video compression macrocells using low-swing differential logic

Improving the performance of fully dedicated macrocells is key to realizing HDTV-resolution video de/compression LSIs operating at more than 100 MHz, having reasonable power consumption and chip size small enough for consumer applications. Existing circuit techniques are either not sufficiently fast or are area consuming. However, these problems are overcome by using low-swing differential logic to realise such macrocells.<<ETX>>

A low power carry select adder with reduced area

A carry-select adder can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders. This paper proposes a new add-one circuit using the first zero finding circuit and multiplexers to reduce the area and power with no speed penalty. For bit length n=64, this new carry-select adder requires 38 percent fewer transistors than the dual ripple-carry carry-select adder and 29 percent fewer transistors than Changs carry-select adder using single ripple carry adder. This new 64b adder has 3.45 ns delay time at 2.5 V power supply using a 0.25 um CMOS technology.

A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver

This paper proposes a low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line. The pulsed NAND-NOR match-line not only significantly reduces the match-line power by activating only a few match-lines by using NAND cells for several bits but also achieves high speed by using NOR cells for most bits. The charge-recycling search-line driver reduces the search-line power by recycling the charge of search-lines without precharging. The CAM chip with 128/spl times/32 bit is fabricated in a 0.25-/spl mu/m CMOS process with 2.5 V. It dissipates 17.2 fJ/bit/search. It consumes 31% power of the dynamic NOR-type CAM.

14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems

In this paper, we present an energy-efficient CNN processor with 4 key features: (1) a CNN-optimized neuron processing engine (NPE), (2) a dual-range multiplyaccumulate (DRMAC) block for low-power convolution operations, (3) an on-chip memory architecture and a utilization scheme for reducing off-chip memory accesses, (4) kernel data compression for further reducing off-chip memory accesses.

A 250-MHz-2-GHz wide-range delay-locked loop

This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DLL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively.