Hyun-Min Park

A predistortion linearizer using envelope-feedback technique with simplified carrier cancellation scheme for class-A and class-AB power amplifiers

A predistortion linearization method using an envelope-feedback technique is proposed and implemented in this paper. This linearizer compensates the gain and phase nonlinearity of power amplifier (PA) simultaneously by controlling both variable attenuator and phase shifter with the feedback of only the difference signal between input and output envelopes. A new carrier cancellation scheme composed of a minimization circuit, log detector, and vector modulator is also presented. This circuit achieves adaptive control of the linearizer by enabling direct measurement of out-of-band power. It is well suited to a multichannel system where the allocated channels are time variant. The principle of the proposed linearizer is described and simple AM-AM distortion analysis is presented analytically and graphically based on the conceptual schematic diagram. A two-tone test for a class-A PA at 1.855 GHz with frequency spacing of 1 MHz showed intermodulation-distortion reduction of maximum 16 dB and stable operation over 5-dB output power variation up to 4-dB backoff from the saturation power level. The proposed linearizer is also applicable to class-AB PAs without further special adjustments. The adaptation circuit is fully implemented with analog integrated circuits, which can further extend its applicability with the integration technology.

A spline large-signal FET model based on bias-dependent pulsed I-V measurement

A spline large-signal FET model is presented. This includes a quiescent bias dependency to predict nonlinear dynamic behavior of FETs in which self-heating and trap effects are present. The intrinsic device of the model represented by a parallel connection of current and charge sources and the model parameters are extracted from bias-dependent pulsed I-Vs and S-parameters, respectively. The validity of the model is demonstrated by comparing the simulated small-signal S-parameters over a wide bias range with measured data. Nonlinear behaviors of FETs such as P/sub in/ - P/sub out/, third-order intermodulation distortion, and efficiency are also compared.

Demonstration of on-chip appended power amplifier for improved efficiency at low power region

A new power amplifier topology which can achieve improved efficiency at power backoff region is demonstrated in this paper. In this topology, the output stage of the amplifier is appended with a secondary transistor in a parallel way through a 3-port interstage matching circuit and an impedance transforming network. By careful selection of the ratio of device active area, this appended transistor achieves earlier saturation at lower output power level than the output transistor, which is a basic requirement in achieving high efficiency. The power amplifier has been realized with InGaP/GaAs HBT technology and showed efficiency improvement of 81% at output power of 16.7 dBm. The proposed topology enables one-chip integration, hence is very attractive for portable communication terminals.

A novel temperature-dependent large-signal model of heterojunction bipolar transistor with a unified approach for self-heating and ambient temperature effects

A large-signal modeling of power heterojunction bipolar transistor (HBT) is demonstrated for an accurate simulation of self-heating and ambient temperature effects and nonlinear behaviors such as output power, gain expansion, intermodulation distortion (IMD), and adjacent channel power ratio (ACPR). The physical relationship between the device current and the rate of change in the built-in potential with respect to the device temperature has been utilized for a fully electrothermal modeling. To enable an immediate use for a circuit design, the model extraction was done for in-situ output-stage device from two-stage power amplifier (PA) circuit. In each parameter extraction step, measurement data obtained under a consistent environment, which are current-voltage (I-V) at various temperatures and small-signal S-parameters under various bias conditions, have been carefully examined and utilized to relate the meaning of each parameter to the physical principle of the device. Measurements and simulations are compared for the verification of the model under dc condition at various temperatures.

A new predistortion linearizer using envelope-feedback technique for PCS high power amplifier application

A predistortion linearizing method using an envelope-feedback technique is proposed and implemented. This linearizer compensates the gain and phase nonlinearity of the power amplifier at the same time by controlling both variable attenuator and phase shifter with the feedback of only the difference signal between the input and output envelopes. Also a new way to achieve signal cancellation is presented with the combination of a minimization circuit, log detector and vector modulator. A two-tone test for a class-A power amplifier at 1.855 GHz with a frequency spacing of 1 MHz showed an IMD reduction of 16 dB maximum and stable operation over 5 dB output power variation up to 4 dB back-off. The proposed linearizer is also applicable to class-AB and class-B power amplifiers without any special adjustments. The adaptation algorithm is fully implemented with analog ICs, which can further extend its applicability with the integration technology.

A large-signal FET model including thermal and trap effects with pulsed I-V measurements

A large signal FET model is presented. This includes a quiescent bias dependency to predict the non-linear dynamic behavior of a FET where thermal and trap effects are present. The intrinsic device of the model is represented by a parallel connection of non-linear currents and charges. The model parameters are extracted from bias dependent pulsed I-Vs and small-signal S-parameters. Measurements and simulations of pulsed I-Vs and S-parameters have been compared for the verification of the model at various quiescent bias voltages. Also load-pull measurement results, including the output power and PAE, have been compared to the simulation results for the validation of the non-linear behavior of the model.

A nonquasi-static table-based small-signal model of heterojunction bipolar transistor

A nonquasi-static table-based (NQS-TB) small-signal model, which has been used successfully in modeling FETs, is applied to a heterojunction bipolar transistor (HBT). The capacitive couplings associated with base cause the conventional model to be invalid at high frequencies. To take these effects into account, a new model is proposed that is compatible with a small-signal T-model topology. We demonstrate good agreement between the measured and simulated S-parameters over the range of 1-40 GHz.

Thermal characteristics of InGaP/GaAs HBT ballasted with extended ledge

A InGaP/GaAs heterojunction bipolar transistor structure is proposed in which the base epi-layer underneath the extended ledge works as a base ballast resistor. The structure eliminates the critical alignment for a passivation ledge formation as well as additional process steps for external base ballast resistors. Both ballasted and unballasted devices were fabricated and compared. A small signal equivalent circuit gives us the magnitude of the effective ballast resistance. The thermal characteristics, including gain-collapsed I-V and V/sub be/ regression curve are shown and modeled. The temperature dependency of base sheet resistance and its influence on the device performance are also discussed.

An Accurate Determination of Thermal Resistance of HBT Based on Pulsed Current I-V Measurement

A method to determine the thermal resistance (Rth) of HBTs is proposed and presented in this paper. The principle of this method is based on the current gain (ß) decrease of HBTs either from ambient temperature rise or internal DC power dissipation. The conventional pulsed I-V setup is modified to pulsed current I-V setup, where the input port of the device is stimulated by constant current rather than constant voltage. By using this setup, two main mechanisms causing the current gain decrease were effectively separated, which was not apparent in the previous methods. The proposed method was applied to find Rth s of various HBT s with different number of emitter fingers. The data agree very well with the predicted thermal resistances of larger emitter area devices by scaling with the total emitter area. Also the measurements with different pulse widths were employed to extract thermal time constant of HBT.

Characterization and modeling of intermodulation distortion asymmetry in HBT using large-signal model

Asymmetrical behaviors of intermodulation distortion (IMD) in microwave active devices are often observed when the terminating impedance at baseband frequency contains a reactive component. This phenomenon sometimes induces misunderstanding of distortion performance unless the baseband impedance effects are properly accounted for. The distortion asymmetry appears in not only small-signal regime but also large-signal regime. Therefore, a unified approach which can predict IMD asymmetry over a broad range of output power levels is in critical demand. In this context, the usefulness of nonlinear large-signal model is addressed when predicting IMD asymmetries. Extensive measurement results are compared to simulation results to demonstrate the usefulness. Moreover, the origin of distortion asymmetry is discussed with time-domain envelope simulation.