Sangsoo Ko

Design and Analysis of a Cascode Bipolar Low-Noise Amplifier With Capacitive Shunt Feedback Under Power-Constraint

A cascode bipolar low-noise amplifier (LNA) with capacitive shunt feedback has been developed to present a solution for simultaneous noise and power match when the real part of the optimum source impedance is not 50 Ω in order to keep high current density under power constraint. The proposed LNA also has the capability for the simultaneous improvement of noise figure (NF) and linearity. In addition, we analyzed and verified that the second-order interaction, which affects the third-order nonlinearity, becomes less sensitive to the low-frequency input termination at higher bias currents. The possibility of removing the low-frequency LC trap is investigated based on this analysis. We also show that LNAs with smaller base and/or smaller emitter resistances require lower source impedance at low frequencies to improve linearity by the same amount. Finally, prudent layouts for improving the performance of the LNA are considered. Eleven design examples of the proposed LNA, which individually operate at 880, 1575, or 1960 MHz, are fabricated in a low-cost 0.35- μm SiGe BiCMOS process to verify the design and analysis experimentally. The fabricated LNAs have excellent performances, especially in NF. For example, the 880-MHz LNA has an NF of 0.9 dB, a power gain of 16 dB, and an IIP3 of +14 dBm with current consumption of 11 mA from a 2.8-V power supply.

Dual-Path

This letter describes a dual-path LC voltage controlled oscillator (VCO) design that reduces both coarse-tuning and fine-tuning sensitivities. By using a combination of discrete and continuous tuning methods for the coarse-tuning control, a very high gain ratio between the coarse-tuning path and the fine-tuning path can be avoided, significantly alleviating noise and coupling problems due to high coarse-tuning gain. A 3.03-3.67 GHz dual-path VCO in 65 nm CMOS exhibits -120.7 dBc/Hz at a 400 kHz offset from a 1.73 GHz carrier, showing better performance than the conventional single-path VCO that is implemented for comparison.

LC

To meet ever-growing demands for higher mobile data-rates, LTE standards continue to evolve. While carrier aggregation (CA) improves data-rates, it requires wider aggregated signal bandwidth that limits the number of users that can be serviced. Techniques like 256QAM and 4×4 MIMO are attractive because improvements do not need wider signal bandwidth. To support 256QAM and 4×4 MIMO for the 5GHz band, we need IPN better than −48dBc or 155fsec rms. A digital fractional-N PLL that achieves 137fsec rms jitter integrating from 10kHz to 10MHz (or 142fsec 1kHz to 10 MHz) with a −78.6dBc near integer-N fractional spur is presented. We have introduced a TDC chopping technique, fine-conversion through SARADCs and TDC nonlinearity calibration to improve IPN and fractional spurs.

VCO Design With Partitioned Coarse-Tuning Control in 65 nm CMOS

In this paper, an ultra-wideband (UWB) upconverter is proposed that has automatic self-calibrating circuits for the in-phase/quadrature mismatch correction and the local (LO) leakage suppression. The proposed self-calibrating circuits have been devised to have UWB functionality without help of the baseband processor. In addition, calibrating circuits do not need any additional analog-to-digital converter or sample-and-hold capacitors that are used to store and update the minimum power because the proposed calibrators find the solution from informations in current state. To verify the performance, the upconverter was applied to an UWB transmitter (Tx), operating from 3.1 to 4.8 GHz and from 6.3 to 9 GHz in 65-nm CMOS. The measured data shows UWB performance for the sideband rejection up to 9 GHz and the LO leakage suppression up to 5 GHz, respectively. The automatically calibrated Tx has error vector magnitude of lower than -20 dB, output 1-dB compression point of -6 dBm, LO leakage of lower than -43 dBm, and sideband suppression ratio of higher than 45 dBc with current consumption of 175 mA from a 1.2-V power supply for all supporting bands and time frequency codes defined in WiMedia UWB specifications.

24.8 A 14nm fractional-N digital PLL with 0.14ps rms jitter and −78dBc fractional spur for cellular RFICs

This paper presents a low-noise ΔΣ fractional-N PLL utilizing a mixed-mode triple-input LC VCO. An analog dual-path VCO control relaxes the nonlinearity problem of the ΔΣ fractional-N PLL, while a combination of discrete and continuous tuning methods for coarse-tuning control significantly alleviates the noise coupling problem caused by the high gain coarse-tuning path. A 3.6GHz ΔΣ fractional-N PLL implemented in 65nm CMOS exhibits nearly −100dBc/Hz in-band noise contribution and −53dBc in-band fractional spur performances from a 1.8GHz carrier.

Design and Analysis of an Ultra-Wideband Automatic Self-Calibrating Upconverter in 65-nm CMOS

An Ultra-wideband (UWB) transmitter is proposed that can correct phase errors in quadrature local (LO) signals automatically without help of baseband processor (BBP), operating from 3 to 9 GHz in 65 nm CMOS. The measured tuning range for sideband rejection is 32.7 dB at 7.7 GHz and 13.6 dB at 8.7 GHz. The measured EVM is lower than −20 dB for all supporting bands and TFCs (Time frequency codes) that are prescribed by WiMedia alliance. The power consumption of the transmitter including LO path and PLLs is 210 mW from a 1.2 V supply.

Low-noise fractional-N PLL design with mixed-mode triple-input LC VCO in 65nm CMOS

A fully integrated, very-low phase-noise CMOS voltage controlled oscillator (VCO) has been implemented for zero-IF CDMA cellular receiver (Rx) using CMOS transistors in a 0.5mum SiGe BiCMOS process technology. To optimize the phase noise performance, the VCO used the proposed coarse and fine tune branch which employed high-Q accumulation-mode MOS (AMOS) varactors. The measured phase noise is below -133dBc/Hz at 900kHz offset frequency from a 1.762GHz carrier, which yields enough margin for the IS-98 single-tone test requirement. The integrated CDMA cellular Rx including this Rx VCO shows more than 2.5dB single-tone performance margin

An Ultra-wideband transmitter with automatic self-calibration of sideband rejection up to 9 GHz in 65nm CMOS

Digital PLL design challenges for cellular RFICs are presented. 5 digital PLLs are integrated in 28nm CMOS to support 3-Rx carrier aggregation (CA)/2-TxCA of FD-LTE/TD-LTE, GSM/EDGE, WCDMA/HSPA, and TD-SCDMA. The 400 kHz fractional spur of GSM/EDGE Tx LO is < −68 dBc for all channels. The integrated phase noise (IPN) degradation due to DCO-to-DCO coupling is < 0.5 dB even if two fractional PLLs are locked at same frequency.

A CMOS VCO with Optimized Tune Branches for Zero-IF CDMA Cellular Application in a 0.5μm BiCMOS process

A low-noise and high-gain ultra wideband (UWB) receiver was developed using a 65nm CMOS technology and a wafer-level fabricated package. In order to enhance the gain and noise figure over a wide frequency band, the resistive feedback amplifier and two cascode stages with the inductive load resonating at three different frequencies are employed. The fabricated UWB receiver showed a high gain of 72.6 dB ± 0.7 dB overall operating frequency range, and an average noise figure of 4.1 dB in 3168 to 4752 MHz, 4.3 dB in 6366 to 7920 MHz and 5.1 dB in 7392 to 8976 MHz frequency band, respectively. The noise figure at high frequency edge is lower than 6 dB. The measured sensitivities in three band groups meet all WiMedia PHY specifications.

Digital PLL design challenges for cellular RFICs

A 3.1–4.7GHz and 6.3–9GHz RF transmitter fabricated in a 65nm CMOS technology and packaged with a Wafer-level Fabricated Package (WFP) is presented. For high frequency and wideband performances, all the effects of package are considered and loopback paths with a power detector are implemented. A new structure of T/R switch is devised for the low noise performance of Rx and the high linearity of Tx. With these circuits, the transmitter features high linearity, low power consumption and small chip area meeting all the WiMedia PHY spec.