Hyun-Mo Koo

Floating gated silicon-on-insulator nonvolatile memory devices with Au nanoparticles embedded in SiO1.3N insulators by digital sputtering method

Floating gated silicon-on-insulator nonvolatile memory devices with Au nanoparticles embedded in SiO1.3N insulators were fabricated. The tunneling SiO1.3N insulator, Au nanoparticles, and control SiO1.3N insulator were sequentially deposited by digital sputtering method at 300°C. The size of Au nanoparticles was controlled in the range of 1–5nm by adjusting the deposition thickness of Au layer and the density of Au nanoparticles was approximately 1.5×1012cm−2. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of Au particles and the memory window was larger than 2.5V.Floating gated silicon-on-insulator nonvolatile memory devices with Au nanoparticles embedded in SiO1.3N insulators were fabricated. The tunneling SiO1.3N insulator, Au nanoparticles, and control SiO1.3N insulator were sequentially deposited by digital sputtering method at 300°C. The size of Au nanoparticles was controlled in the range of 1–5nm by adjusting the deposition thickness of Au layer and the density of Au nanoparticles was approximately 1.5×1012cm−2. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of Au particles and the memory window was larger than 2.5V.

A fully roll-to-roll gravure-printed carbon nanotube-based active matrix for multi-touch sensors.

Roll-to-roll (R2R) printing has been pursued as a commercially viable high-throughput technology to manufacture flexible, disposable, and inexpensive printed electronic devices. However, in recent years, pessimism has prevailed because of the barriers faced when attempting to fabricate and integrate thin film transistors (TFTs) using an R2R printing method. In this paper, we report 20 × 20 active matrices (AMs) based on single-walled carbon nanotubes (SWCNTs) with a resolution of 9.3 points per inch (ppi) resolution, obtained using a fully R2R gravure printing process. By using SWCNTs as the semiconducting layer and poly(ethylene terephthalate) (PET) as the substrate, we have obtained a device yield above 98%, and extracted the key scalability factors required for a feasible R2R gravure manufacturing process. Multi-touch sensor arrays were achieved by laminating a pressure sensitive rubber onto the SWCNT-TFT AM. This R2R gravure printing system overcomes the barriers associated with the registration accuracy of printing each layer and the variation of the threshold voltage (Vth). By overcoming these barriers, the R2R gravure printing method can be viable as an advanced manufacturing technology, thus enabling the high-throughput production of flexible, disposable, and human-interactive cutting-edge electronic devices based on SWCNT-TFT AMs.

Scalability of carbon-nanotube-based thin film transistors for flexible electronic devices manufactured using an all roll-to-roll gravure printing system.

To demonstrate that roll-to-roll (R2R) gravure printing is a suitable advanced manufacturing method for flexible thin film transistor (TFT)-based electronic circuits, three different nanomaterial-based inks (silver nanoparticles, BaTiO3 nanoparticles and single-walled carbon nanotubes (SWNTs)) were selected and optimized to enable the realization of fully printed SWNT-based TFTs (SWNT-TFTs) on 150-m-long rolls of 0.25-m-wide poly(ethylene terephthalate) (PET). SWNT-TFTs with 5 different channel lengths, namely, 30, 80, 130, 180, and 230 μm, were fabricated using a printing speed of 8 m/min. These SWNT-TFTs were characterized, and the obtained electrical parameters were related to major mechanical factors such as web tension, registration accuracy, impression roll pressure and printing speed to determine whether these mechanical factors were the sources of the observed device-to-device variations. By utilizing the electrical parameters from the SWNT-TFTs, a Monte Carlo simulation for a 1-bit adder circuit, as a reference, was conducted to demonstrate that functional circuits with reasonable complexity can indeed be manufactured using R2R gravure printing. The simulation results suggest that circuits with complexity, similar to the full adder circuit, can be printed with a 76% circuit yield if threshold voltage (Vth) variations of less than 30% can be maintained.

Improvement of charge storage characteristics on floating gated nonvolatile memory devices with In2O3 nanoparticles embedded polyimide gate insulator

Nanofloating gate memory (NFGM) devices using In2O3 nanoparticles as charge storages embedded in polyimide gate insulator were fabricated. Self-assembled In2O3 nanoparticles were formed inside the polyimide matrix as a result of chemical reactions between indium ions and polymer precursors. The average diameter and the particle density were 7nm and 6×1011cm−2, respectively. The memory window of fabricated NFGM device due to the charging effect of In2O3 particles was larger than 4.4V. The charge storage characteristics of NFGM devices with In2O3 nanoparticles embedded in polyimide gate insulator were significantly improved by the postannealing in a 3% diluted hydrogen in N2 ambient.

Characterization of thiol-functionalized oligo(phenylene-ethynylene)-protected Au nanoparticles by scanning tunneling microscopy and spectroscopy

The electrical properties of Au nanoparticles protected by thiol-functionalized oligo(phenylene-ethynylene) (OPE), 1,4-bis-(3-mercapto-phenylethynyl)benzene have been investigated by scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS). The STM and scanning electron microscopy images of chemisorbed OPE-protected Au nanoparticles on Au(111) surface were similar, and the densities were almost identical. OPE-protected Au nanoparticles exhibited stochastic conductance switching behaviors, and current-voltage (I–V) and log I–V characteristics by STS at 100 K showed Coulomb blockade behaviors. The charging energy of Au nanoparticles was as high as 0.57 eV when the core diameter was 2.1 nm. Our results are significant for single-electron transistor memory applications.

Fabrication of Low Temperature Polycrystalline Silicon Thin-Film Transistor Nonvolatile Memory Devices for Digital Memory on Glass Applications

We fabricated the nano-floating gate memory (NFGM) devices on the polycrystalline silicon (poly-Si) films crystallized by excimer laser annealing (ELA) method for thin-film transistor liquid-crystal display (TFT-LCD) with a new integration technology called digital memory on glass (DMOG). The In2O3 nano-dots were formed in polyimide gate insulating layers at low temperature as the charge storages of nonvolatile memory for DMOG applications. The memory window of low temperature poly-Si TFT nonvolatile memory with In2O3 nano-dots embedded in polyimide was larger than 3.2 V and the memory characteristics were considerably improved by 3% hydrogen diluted N2 ambient annealing.

Electrical Characterization of Nano-Floating Gated Silicon-on-Insulator Memory with In2O3 Nano-Particles Embedded in Polyimide Insulator

We fabricated the floating gate for silicon-on-insulator nonvolatile memory devices with In2O3 nano-particles embedded in polyimide insulator. Self-assembled In2O3 nano-particles were created by chemical reaction between the biphenyl dianhydride-p-phenylenediamine polymer precursor and indium films. The particles size and density of In2O3 nano-particles were 7nm and 6×1011cm-2, respectively. The current-voltage and retention time of fabricated device were characterized by using semiconductor parameter analyzer. A significant threshold voltage shift of fabricated nano-floating gate memory devices obtained, because of the charging effects of In2O3 nano-particles. And a memory window measured about 1V at initial status.

Improvement of Carrier Mobility on Silicon-Germanium on Insulator MOSFET Devices with a Strained-Si Layer

The effects of heat treatment on the electrical properties of strained-Si/SiGe-on-insulator (SGOI) devices were examined. We proposed the optimized heat treatment processes for improving the back interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA (rapid thermal annealing) before gate oxidation step and the post-RTA after source/drain dopant activation step, the electrical properties of strained-Si channel on layer were greatly improved, which resulting the improvement of the driving current, transconductance, and leakage current of SGOI-MOSFET.

Fabrication of SOI FinFET Devices using Arsenic Solid-phase-diffusion

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the -p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.