Hyunchul Seok

Efficient page caching algorithm with prediction and migration for a hybrid main memory

Emerging next generation memories, NVRAMs, such as Phase-change RAM (PRAM), Ferroelectric RAM (FRAM), and Magnetic RAM (MRAM) are rapidly becoming promising candidates for large scale main memory because of their high density and low power consumption. Many researchers have attempted to construct a main memory with NVRAMs, in order to make up for the limits of NVRAMs. However, we find that the preexisting page caching algorithms, such as LRU, LIRS, and CLOCK-Pro, are often sub-optimal for NVRAMs due to its DRAM-oriented design including uniform access latency and unlimited endurance. Consequently, the algorithms cannot be directly adapted to the hybrid main memory architecture with PRAM. To mitigate this design limitation, we propose a new page caching algorithm for the hybrid main memory. It is designed to overcome the long latency and low endurance of PRAM. On the basis of the LRU replacement algorithm, we propose a prediction of page access pattern and migration schemes to maintain write-bound access pages to DRAM. The experiment results have convinced us that our page caching algorithm minimizes the number of the write access of PRAM while maintaining the cache hit ratio. The results show that we can reduce the total write access count by a maximum of 52.9% and the consumed energy by 19.9%. Therefore, we can enhance the average page cache performance and reduce the endurance problem in the hybrid main memory.

Migration based page caching algorithm for a hybrid main memory of DRAM and PRAM

As the DRAM based main memory significantly increases the power and cost budget of a computer system, new memory technologies such as Phase-change RAM (PRAM), Ferroelectric RAM (FRAM), and Magnetic RAM (MRAM) have been proposed to replace the DRAM. Among these memories, PRAM is the most promising candidate for large scale main memory because of its high density and low power consumption. In previous researches, a hybrid main memory approach of DRAM and PRAM is adopted to make up for the latency and endurance limits of PRAM. On the other hand, large amount of a main memory is used for page cache to hide disk access latency. Many page caching algorithms such as LRU, LIRS, and CLOCK-Pro are developed and show good performance, but these are only consider the main memory with uniform access latency and unlimited endurance. They cannot be directly adapted to the hybrid main memory architecture with PRAM. In this paper, we propose a new page caching algorithm for the hybrid main memory. It is designed to overcome the long latency and low endurance of PRAM. On the basis of the LRU replacement algorithm, we propose page monitoring and migration schemes to keep read-bound access pages to PRAM. The experiment results show that our page caching algorithm minimize the write access of PRAM while maintaining cache hit ratio. The results show that we can maximally reduce the total write access count by 48.4%. Therefore, we can enhance the average page cache performance and reduce the endurance problem in the hybrid main memory.

pKASSO: Towards Seamless Authentication Providing Non-Repudiation on Resource-Constrained Devices

PKI is generally considered as the most appropriate solution for e-commerce and mutual authentication, owing to its digital signature and non-repudiation features. Asymmetric key operations of PKI require by far more CPU cycles than a symmetric cryptographic algorithm. It hampers the usability of PKI on resource-constrained devices. To overcome these limitations, we propose a new PKI- based authentication protocol and security infrastructure enhanced with single sign-on and delegation technology for a device with a restricted computing power. Although a conventional delegation mechanism cannot support non-repudiation mechanism against malicious users behavior, our proposed protocol and security infrastructure can provide the mechanism by devising a referee server that generates binding information between a device and authentication messages, and retains the information in its local storage for future accusation.

MN-MATE: Elastic Resource Management of Manycores and a Hybrid Memory Hierarchy for a Cloud Node

Recent advent of manycore system increases needs for larger but faster memory hierarchy. Emerging next generation memories such as on-chip DRAM and nonvolatile memory (NVRAM) are promising candidates for replacement of DRAM-only main memory. Combined with the manycore trends, it gives an opportunity to rethink conventional resource management system with a memory hierarchy for a single cloud node. In an attempt to mitigate the energy and memory problems, we propose MN-MATE, an elastic resource management architecture for a single cloud node with manycores, on-chip DRAM, and large size of off-chip DRAM and NVRAM. In MN-MATE, the hypervisor places consolidated VMs and balances memory among them. Based on the monitored information about the allocated memory, a guest OS co-schedules tasks accessing different types of memory with complementary access intensity. Polymorphic management of DRAM hierarchy accelerates average memory access speed inside each guest OS. A guest OS reduces energy consumption with small performance loss based on the NVRAM-aware data placement policy and the hybrid page cache. A new lightweight kernel is developed to reduce the overhead from the guest OS for scientific applications. Experiment results show that our techniques in MN-MATE platform improve system performance and reduce energy consumption.

Efficient memory management of a hierarchical and a hybrid main memory for MN-MATE platform

The advent of manycore in computing architecture causes severe energy consumption and memory wall problem. Thus, emerging technologies such as on-chip memory and nonvolatile memory (NVRAM) have led to a paradigm shift in computing architecture era. For instance, nonvolatile memories like PRAM can be viable DRAM replacements, achieving competitive speeds at lower power consumption. On-chip memory such as 3D-stacked memory can solve the limitation of memory bandwidth. The confluence of these trends offers a new opportunity to rethink traditional computing system and memory hierarchies. In an attempt to mitigate the energy and memory wall, we propose a new architecture with a hierarchical and a hybrid main memory for manycore system, termed MN-MATE. The hierarchical memory consists of on-chip memory, which is called M1 memory, and a conventional DRAM memory is replaced by a hybrid memory of DRAM and PRAM, called M2 memory. On the top of the system, we designed and evaluated efficient management techniques to achieve the high performance and the low energy usage, including hierarchical memory management, power-aware hybrid memory management, and file caching on a hybrid memory. Preliminary results show that these techniques can improve performance and reduce energy usage. As a case study, we introduce the MaaS (Matching-as-a-Service) application which requires the large amount of memory and high computing power.

Resource Management of Manycores with a Hierarchical and a Hybrid Main Memory for MN-MATE Cloud Node

The advent of manycore in computing architecture causes severe energy consumption and memory wall problem. Emerging technologies such as on-chip DRAM and nonvolatile memory (NVRAM) receive attention as promising solutions for them. Nonvolatile memory is a viable DRAM replacement, achieving competitive performance at lower power consumption. On-chip DRAM extends the memory bandwidth. The confluence of these trends offers a new opportunity to rethink traditional computing system and memory hierarchies. In an attempt to mitigate the energy and memory wall, we propose MN-MATE, a novel architecture and management techniques for resource allocation of a number of cores, onchip DRAM, and large size of off-chip DRAM and NVRAM. In MN-MATE, each guest OS utilizes cores and various memories allocated by the hypervisor. Based on the knowledge about the allocated resources, a guest OS co-schedules tasks accessing different types of memory with complementary access intensity. Memory management system of the OS utilizes on-chip DRAM as a part of main memory having low latency. It also selects proper location of data from the three types of memory based on the datas access characteristics. Preliminary experimental results show that these techniques with the new architecture improve system performance and reduce energy consumption.

PRAM wear-leveling algorithm for hybrid main memory based on data buffering, swapping, and shifting

We propose a novel wear-leveling algorithm for the hybrid main memory architecture which exploits both fast read and write speed of DRAM and low power consumption and high density of PRAM. The wear-leveling algorithm consists of three techniques: DRAM buffering for reducing the write count, multiple data swapping for evening out the write count among all pages, and data shifting evening out the write count among all pages and lines. In order to evaluate performance, we implement a PIN-based wear-leveling simulator. In SPEC CPU2006, our proposed schemes can reduce the write count and maintain the write count equally among all pages and lines with little additional overhead.

An adaptive update-rate control of a phased array radar for efficient usage of tracking tasks

In multi-functional radar, task scheduling algorithm should be designed such that timing resource is efficiently utilized by functions such as surveillance and tracking, and its performance is maximized. In the target tracking, the tasks are required to be executed to consider the maneuvering motion, measurement condition and required tracking performance. Frequent execution of tracking tasks results in not only precise tracking, but also waste of timing resource which is shared with other functions. Therefore, to reduce the number of unnecessary observations, the tracking task is required to be executed only when the update is needed. In this paper, the innovation, position residual, in Kalman filter is used as reference value for adjusting update rate of tracking tasks. Using feedback controller, the update rate is allocated so that predicted observation is expected to be within specified error range. In addition, targets are classified into 7 priorities according to tactical characteristics, and targets priority is also used as reference value for calculating update rate. The simulation results show that the proposed method reduces the tracking error of the target on maneuvering movement compared to fixed update rate case.

PokerFace: Game players themselves are truly memorable

Video games support instant replays so that game players can see previously occurred events (e.g., goals in sports games) again from a different point of view and permanently store such exciting moments and feelings as pleasant memories. However, players are likely to have different feelings and enjoyment depending on the player context, such as who they play with, their looks, or conversation during gaming even for the same game. Therefore, instant replays without such player context are not enough for users to remind the enjoyable moments that could not happen again, and thus precious memories will be forgotten. This paper presents PokerFace, a new video game console that provides advanced instant replays containing the player context. PokerFace detects memorable situations during gaming and generates advanced instant replays by combining both the game replay and the users reaction and synchronizes them in time so that the players can see both their own looks and those of other players at the time when the exciting moment take place. Our system provides game players with better memories by storing advanced instant replays into the permanent storage or web blogs. We have implemented a prototype of PokerFace and conducted user studies. From the evaluation results, we conclude that PokerFace can have the competitiveness in game consoles market by giving more enjoyment and better memories for users.