Hyungjun Cho

A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction

The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate.

A Survey of Repair Analysis Algorithms for Memories

Current rapid advancements in deep submicron technologies have enabled the implementation of very large memory devices and embedded memories. However, the memory growth increases the number of defects, reducing the yield and reliability of such devices. Faulty cells are commonly repaired by using redundant cells, which are embedded in memory arrays by adding spare rows and columns. The repair process requires an efficient redundancy analysis (RA) algorithm. Spare architectures for the repair of faulty memory include one-dimensional (1D) spare architectures, two-dimensional (2D) spare architectures, and configurable spare architectures. Of these types, 2D spare architectures, which prepare extra rows and columns for repair, are popular because of their better repairing efficiency than 1D spare architectures and easier implementation than configurable spare architectures. However, because the complexity of the RA is NP-complete, the RA algorithm should consider various factors in order to determine a repair solution. The performance depends on three factors: analysis time, repair rate, and area overhead. In this article, we survey RA algorithms for memory devices as well as built-in repair algorithms for improving these performance factors. Built-in redundancy analysis techniques for emergent three-dimensional integrated circuits are also discussed. Based on this analysis, we then discuss future research challenges for faulty-memory repair studies.