Wooheon Kang

A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction

The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate.

A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories

3-D-stacked memory using through-silicon-vias (TSVs) has emerged as a good alternative for overcoming the limitation of 2-D memory technology. Among many issues with 3-D-stacked memory, yield is one of the major challenges for mass production. This paper proposes a new fuse architecture and redundancy scheme to improve the yield of 3-D-stacked memories. The new fuse architecture is developed based on the fact that the unused redundancies in prebond repair cause the inefficiency. Therefore, the new fuse architecture provides a way to share redundancies in prebond and postbond repairs. There are two kinds of operation modes. One is an enable mode for collecting the used redundancy information. The other is a mask mode for obtaining faulty redundancy information using a short test algorithm. Using the new fuse architecture, a new redundancy scheme called the post-share scheme is developed to achieve optimal yield. The post-share scheme allocates the fixed number of spare rows and columns for each repair just like other schemes. However, only allocated redundancies are used in prebond repair, while both the redundancies allocated for postbond repair and unused redundancies in prebond repair can be used for postbond repair. Experimental results show that the post-share redundancy scheme significantly increases the final yield of 3-D-stacked memories and the increase of area overhead is small.

A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories

A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 × 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55% of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.

EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate

Faulty cell repair with redundancy can improve memory yield. In particular, built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. We propose an efficient BIRA algorithm to achieve the optimal repair rate with a very short analysis time and low hardware cost. The proposed algorithm can significantly reduce the number of backtracks in the exhaustive search algorithm: it uses early termination based on the number of orthogonal faulty cells and fault classification in fault collection. Experimental results show that the proposed BIRA methodology can achieve optimal repair rate with low hardware overhead and short analysis time, as compared to previous BIRA methods.

A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories

Three-dimensional (3-D) memories using through-silicon-vias (TSVs) as vertical buses across memory layers has regarded as one of 3-D integrated circuits (ICs) technology. The memory dies to stack together in a 3-D memory are selected by a die selection method. In order to improve yield of 3-D memories, redundancy sharing between inter-die using TSVs is an effective strategy. With the redundancy sharing strategy, the bad memory dies can become good 3-D memories through matching the good memory dies. To support die selection and matching efficiently, a novel redundancy analysis (RA) algorithm, which considers various repair solutions, is proposed. Because the repair solutions can be various, the proposed die selection and matching is performed with two stages; general die selection and matching method in the first stage and re-matched remained memory dies, after the first stage, applying other repair solutions in the second stage. Thus, the proposed die selection and matching algorithm using the proposed RA algorithm can improve yield of 3-D memories. The experimental results show that the proposed die selection and matching method can achieve higher yield of 3-D memories than that of the previous state-of-the-art the die selection and matching methods.

A New Accelerated Endurance Test for Terabit NAND Flash Memory Using Interference Effect

Limited endurance of E/W cycles is a unique restriction of flash memories and the endurance characteristics usually take a longer time to test. In this paper, we proposed a novel endurance test scheme that takes advantage of the parasitic cell-to-cell interference as well as a shortened program time to accelerate the endurance test for terabit NAND flash memory. The novelty of the new scheme is the use of a new test sequence known as even/odd row address sequence (EORAS). The interference effect during the program operation mainly affects the threshold voltage widening in the victim cell and leads to errors linearly during the read operation. We mainly focus on the correlation between the interference and device error rate during the endurance test. Based on the correlation, we use the interference effect as an acceleration factor in EORAS. EORAS is composed of a new program operation for unit test-time reduction. Our experimental results show that the proposed scheme method can induce the raw bit error rate by 50% and thereby improve the cycling time by 19.4% in a 3×-nm flash device. The proposed scheme method can also induce the raw bit error rate by 80% and thereby improve the endurance test time by 30.8% in a 2×-nm flash device. Consequently, the new endurance scheme reduces the test time by 68.4%.

Scan cell reordering algorithm for low power consumption during scan-based testing

Power consumption during scan-based testing can be higher than that of normal mode operations, which can cause yield loss and degradation of reliability. This paper proposes a scan cell reordering algorithm to reduce the test power consumption during scan-based testing. The proposed algorithm considers both shift-out operations and shift-in operations. A cumulative weighted transition (CWT) is proposed and compared to minimize the test power consumption. Experimental results show that the proposed method greatly reduces the average power during scan testing.

Enhenced redundancy analysis for memories using geometric faults based search tree

With the growth of memory capacity and density, test cost and yield improvement are becoming more important. To increase yield of memory, redundancy analysis (RA) which analyzes the faults in memory is essential. However, the time for finding solutions to repair memories with faulty cells is very huge because most RA algorithms for automatic test equipment (ATE) are based on a tree structure. To reduce the time of memory test & repair is important to increase the memory yield using ATE. In order to reduce the time of memory test & repair, an RA algorithm with an early termination condition is proposed and it builds a geometric faults based search tree. To build the proposed algorithm, the faults in a memory are classified into geometric faults according to their characteristic. The experimental results show the effectiveness of the proposed algorithm.