Hyungseup Kim

Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Fully Integrated Biopotential Acquisition Analog Front-End IC

A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 µm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm2. A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 µVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

Low-Power and Low-Noise Capacitive Sensing IC Using Opamp Sharing Technique

This letter presents a low-power and low-noise capacitive sensing IC using opamp sharing technique. The proposed IC reduces both the power consumption and the required circuit area using the opamp sharing technique while maintaining low noise characteristics. A correlated double sampling technique is adopted to reduce the low-frequency noise, including the 1/f noise. An automatic offset calibration loop can automatically reduce the offset parasitic capacitance in the range from -10.8 to +10.8 pF. The power consumption and the active circuit area are 1.02 mW and 2.12 mm2, respectively. The integrated input referred capacitance noise is 0.164 aFRMS with a bandwidth of 400 Hz.

Reconfigurable Sensor Analog Front-End Using Low-Noise Chopper-Stabilized Delta-Sigma Capacitance-to-Digital Converter

This paper proposes a reconfigurable sensor analog front-end using low-noise chopper-stabilized delta-sigma capacitance-to-digital converter (CDC) for capacitive microsensors. The proposed reconfigurable sensor analog front-end can drive both capacitive microsensors and voltage signals by direct conversion without a front-end amplifier. The reconfigurable scheme of the front-end can be implemented in various multi-mode applications, where it is equipped with a fully integrated temperature sensor. A chopper stabilization technique is implemented here to achieve a low-noise characteristic by reducing unexpected low-frequency noises such as offsets and flicker noise. The prototype chip of the proposed sensor analog front-end is fabricated by a standard 0.18-μm 1-poly-6-metal (1P6M) complementary metal-oxide-semiconductor (CMOS) process. It occupies a total active area of 5.37 mm2 and achieves an effective resolution of 16.3-bit. The total power consumption is 0.843 mW with a 1.8 V power supply.

Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications

BACKGROUND Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. OBJECTIVE This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. METHODS Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). RESULTS The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. CONCLUSIONS The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

Low noise resistive analog front-end with automatic offset calibration loop

This paper presents a low noise resistive analog front-end (AFE) with automatic offset calibration loop. The capacitive transimpedance amplifier (CTIA) with correlated double sampling (CDS) technique is adopted to achieve low noise characteristics. The AFE employs automatic offset calibration loop (AOCL) to reduce the offset variations due to the fabrication imperfections. The automatic offset calibration loop is implemented using successive approximation register (SAR) logic and binary-weighted current-mode digital-to-analog converter (DAC). The analog output tracks the reference voltage using the binary search algorithms. The AFE is fabricated in 0.18μm 1P6M CMOS process. The core chip size of the AFE without I/O p-ad s is 1.76 mm2.