I-Chun Cheng

Silicon for thin-film transistors

We are standing at the beginning of the industrialization of flexible thin-film transistor (TFT) backplanes. The two important research directions for the TFTs are (i) processability on flexible substrates and (ii) sufficient field-effect mobilities of electrons and holes to support complementary metal insulator semiconductor operation. The most important group of TFT capable semiconductors are the several modifications of silicon films: amorphous, nanocrystalline and microcrystalline. We summarize their TFT properties and their compatibility with foil substrate materials.

Hole and electron field-effect mobilities in nanocrystalline silicon deposited at 150 °C

Field-effect structures were made from nanocrystalline silicon (nc-Si:H) deposited at a substrate temperature of 150 °C by plasma-enhanced chemical vapor deposition excited at 80 MHz. The nc-Si:H channel layer was grown on top of a separate nc-Si:H buffer and seed layer that serves to develop the crystalline structure. Staggering the contacts and the gate ensures that mobilities are measured precisely in the last-to-grow nc-Si:H layer. The hole mobility in saturation reaches 0.06–0.2 cm2 V−1 s−1 and the electron mobility ∼12 cm2 V−1 s−1. These results suggest that large-area circuits of complementary p- and n-channel devices can be made from nc-Si:H deposited on low-temperature substrates.

Stability of amorphous-silicon TFTs deposited on clear plastic substrates at 250/spl deg/C to 280/spl deg/ C

Amorphous-silicon (a-Si) thin-film transistors (TFTs) were fabricated on a free-standing new clear plastic substrate with high glass transition temperature (T/sub g/) of >315/spl deg/ C and low coefficient of thermal expansion of <10 ppm/ /spl deg/ C. Maximum process temperatures on the substrates were 250/spl deg/C and 280/spl deg/C, close to the temperatures used in industrial a-Si TFT production on glass substrates. The first TFTs made at 280/spl deg/C have dc characteristics comparable to TFTs made on glass. The stability of the 250/spl deg/C TFTs on clear plastic is approaching that of TFTs made on glass at 300/spl deg/C-350/spl deg/C. TFT characteristics and stability depend only on process temperature and not on substrate type.

A single-layer permeation barrier for organic light-emitting displays

Films of a hybrid material with part-SiO2 part-silicone character are deposited as environmental barriers on bottom-emitting and on transparent organic light-emitting diodes. Devices coated with this barrier have lifetimes of up to ∼7500h when stored at 65°C and 85% relative humidity, by far exceeding the industrial requirement of 1000h. The intensity of the Si–O–Si absorption at the wavenumber of 1075cm−1, the wetting angle by water, and the indentation hardness support the interpretation of a homogeneous material with the properties of a SiO2-silicone hybrid. The films remain intact over 58600cycles of bending to ∼0.2% tensile strain.

Rapid Atmospheric Pressure Plasma Jet Processed Reduced Graphene Oxide Counter Electrodes for Dye-Sensitized Solar Cells

In this work, we present the use of reduced graphene oxide (rGO) as the counter electrode materials in dye-sensitized solar cells (DSSCs). rGO was first deposited on a fluorine-doped tin oxide glass substrate by screen-printing, followed by post-treatment to remove excessive organic additives. We investigated the effect of atmospheric pressure plasma jet (APPJ) treatment on the DSSC performance. A power conversion efficiency of 5.19% was reached when DSSCs with an rGO counter electrode were treated by APPJs in the ambient air for a few seconds. For comparison, it requires a conventional calcination process at 400 °C for 15 min to obtain comparable efficiency. Scanning electron micrographs show that the APPJ treatment modifies the rGO structure, which may reduce its conductivity in part but simultaneously greatly enhances its catalytic activity. Combined with the rapid removal of organic additives by the highly reactive APPJ, DSSCs with APPJ-treated rGO counter electrode show comparable efficiencies to furnace-calcined rGO counter electrodes with greatly reduced process time. This ultrashort process time renders an estimated energy consumption per unit area of 1.1 kJ/cm(2), which is only one-third of that consumed in a conventional furnace calcination process. This new methodology thus saves energy, cost, and time, which is greatly beneficial to future mass production.

Two dimensional electron gases in polycrystalline MgZnO/ZnO heterostructures grown by rf-sputtering process

This paper reports the formation of two-dimensional electron gas (2DEG) in rf-sputtered defective polycrystalline MgZnO/ZnO heterostructure via the screening of grain boundary potential by polarization-induced charges. As the MgZnO thickness increases, the sheet resistance reduces rapidly and then saturates. The enhancement of the interfacial polarization effect becomes stronger, corresponding to a larger amount of resistance reduction, when the Mg content in the cap layer increases. Monte Carlo method by including grain boundary scattering effect as well as 2D finite-element-method Poisson and drift-diffusion solver is applied to analyze the polycrystalline heterostructure. The experimental and Monte Carlo simulation results show good agreement. From low temperature Hall measurement, the carrier density and mobility are both independent of temperature, indicating the formation of 2DEG with roughness scattering at the MgZnO/ZnO interface.

Overview of Flexible Electronics Technology

This chapter provides an overview of the history, concepts, and possible applications of flexible electronics from the perspectives of materials and fabrication technology. The focus is on large-area capable electronic surfaces. These are made of backplane and frontplane optoelectronics that are fabricated as fully integrated circuits on flexible substrates. The discussion covers flexible electronics, and reaches back to rigid-substrate precursor technology where appropriate. Flexible electronics is a wide-open and rapidly developing field of research, development, pilot production, and field trials. The chapter puts a perspective on the technology by systematizing it and by describing representative examples.

Enhanced thermoelectric power in dual-gated bilayer graphene.

The thermoelectric power of a material, typically governed by its band structure and carrier density, can be varied by chemical doping that is often restricted by solubility of the dopant. Materials showing large thermoelectric power are useful for many industrial applications, such as the heat-to-electricity conversion and the thermoelectric cooling device. Here we show a full electric-field tuning of thermoelectric power in a dual-gated bilayer graphene device resulting from the opening of a band gap by applying a perpendicular electric field on bilayer graphene. We uncover a large enhancement in thermoelectric power at a low temperature, which may open up a new possibility in low temperature thermoelectric application using graphene-based device.

Mobility Enhancement of Polycrystalline MgZnO/ZnO Thin Film Layers With Modulation Doping and Polarization Effects

ZnO has shown great promise for application in optoelectronic devices, in which the modulation of conductivity is crucial to device performance. In this paper, we have applied the Monte Carlo method to analyze the mobility of single-crystalline and polycrystalline MgZnO/ZnO heterostructure thin film layers. The effects of grain boundary scattering and ionized impurity scattering, as well as phonon scattering, are considered. Our studies show that, with careful design of modulation doping that considers the effects of spontaneous and piezoelectric polarization, the grain boundary potential can be suppressed to improve the mobility of the ZnO layer by at least one order of magnitude. Simulation results are also confirmed by our experimental work, which shows that the polarization effect does play an important role in attracting carriers and increasing the mobility.

Gate-Bias Stress Stability of P-Type SnO Thin-Film Transistors Fabricated by RF-Sputtering

The gate-bias stress stability of p-type tin monoxide (SnO) thin-film transistors (TFTs) is investigated. The SnO TFT exhibits a threshold voltage of 2.5 V, a field-effect hole mobility of 0.24 cm2V-1s-1, a sub-threshold swing of 2 V/decade, and an ON/OFF current ratio of 103. Under gate-bias stress, the transfer characteristics shift with the same polarity as the stress voltage, whereas the sub-threshold swing and field-effect mobility remain almost unaltered. The threshold voltage shifts under various gate-bias stress voltages are well fitted by the stretch-exponential equation. This indicates that the dominant mechanism of the threshold voltage shift is the charge trapping at the interface between the active layer and the gate dielectric or at the gate dielectric near the interface. Larger amounts of threshold voltage shifts observed in the positive gate-bias stress may be caused by the bias-induced adsorption of oxygen on the unpassivated backchannel surface in addition to charge trapping.