I-Chung Chiu

Gate-Bias Stress Stability of P-Type SnO Thin-Film Transistors Fabricated by RF-Sputtering

The gate-bias stress stability of p-type tin monoxide (SnO) thin-film transistors (TFTs) is investigated. The SnO TFT exhibits a threshold voltage of 2.5 V, a field-effect hole mobility of 0.24 cm2V-1s-1, a sub-threshold swing of 2 V/decade, and an ON/OFF current ratio of 103. Under gate-bias stress, the transfer characteristics shift with the same polarity as the stress voltage, whereas the sub-threshold swing and field-effect mobility remain almost unaltered. The threshold voltage shifts under various gate-bias stress voltages are well fitted by the stretch-exponential equation. This indicates that the dominant mechanism of the threshold voltage shift is the charge trapping at the interface between the active layer and the gate dielectric or at the gate dielectric near the interface. Larger amounts of threshold voltage shifts observed in the positive gate-bias stress may be caused by the bias-induced adsorption of oxygen on the unpassivated backchannel surface in addition to charge trapping.

Complementary Oxide–Semiconductor-Based Circuits With n-Channel ZnO and p-Channel SnO Thin-Film Transistors

Fully oxide thin-film transistor (TFT)-based complementary metal-oxide-semiconductor (CMOS) ring oscillators are reported, for the first time, using large-area-compatible sputtering processes. The p-channel tin monoxide (SnO) and n-channel zinc oxide (ZnO) TFTs used in the CMOS inverter have inverted-staggered bottom-gate structures. The SnO TFT exhibits a threshold voltage (Vth) of 3.5 V, field-effect mobility of 0.33 cm2/V-s, subthreshold swing of 2.5 V/decade, and ON/OFF current ratio of ~103. The corresponding values for the ZnO TFT are 6.22 V, 3.5 cm2/V-s, 350 mV/decade, and >106. The achieved voltage gain of the CMOS inverters is ~17 at a supplied voltage (VDD) of 10 V when the geometric aspect ratio is 5. An oscillation frequency of 2 kHz is obtained from a five-stage oxide-based CMOS voltage control oscillator at (VDD) of 14 V.

Two dimensional thermoelectric platforms for thermocapillary droplet actuation

Thermocapillary droplet actuation on a substrate is based on the mechanism that droplets can be driven to the cooler regions via surface tension modulation by varying the temperature. The usual method of providing a temperature gradient or temperature difference for thermocapillary droplet actuation is via resistor heaters, in which the rise in temperature can be achieved by increasing the passing currents, yet the cooling function relies on the natural conduction and/or convection. A thermoelectric (TE) chip is advantageous in the temperature control. The heating and cooling functions can be manipulated simply by adjusting the direction of the input current into the TE chip. In this regard, the temperature setting can be precisely feedback-controlled by manipulating the amplitude and direction of current flows. This paper demonstrates the implementation of a two dimensional (2D) TE array for free-surface thermocapillary droplet actuation. The routing, merging, and cutting of droplets are successfully demonstrated on a hydrophobically patterned glass substrate overlaid on the TE array.

Plasma-etched nanoporous TiO2 using Ag nanoparticle masks: application for photoanodes of dye-sensitized solar cells

We investigate dye-sensitized solar cells (DSSCs) with nanoporous TiO2 photoanodes etched by inductively coupled plasmas (ICPs). Thermally Shrunk Ag nanoparticles are used as the etching masks during the ICP etching procedure. The efficiency of the assembled DSSC increases first and then decreases as the ICP etching time increases. The enhancement of light trapping/scattering is observed after ICP etching with Ag nanoparticle masks, however, over-etching may mitigate the effect. Interfacial charge transfer impedance of TiO2/dye/electrolyte also decreases first and then increases as the etching time increases, a trend highly correlated to the variation of the cell efficiency. Our experimental results indicate that the enhancement of light trapping (which leads to the increase of photocurrent), increase of open circuit voltage and reduction of charge transport resistance lead to the improvement of cell efficiency. The optimized etching time is around 30 s to 1 min. In comparison to the counterpart experiment, the DSSC with TiO2 photoanode etched by ICP without Ag nanoparticle shadow masks, the cell reveals monotonic decreases of photocurrent level, open circuit voltage, and efficiency with the ICP etching time.

Electromechanical Stability of Flexible Nanocrystalline-Silicon Thin-Film Transistors

We have demonstrated inverted staggered bottom-gate back-channel-passivated hydrogenated nanocrystalline-silicon thin-film transistors (TFTs) on colorless polyimide foil substrates. Their electrical performance and stability have been investigated under mechanical flexing. The electron field-effect mobilities and threshold voltages of these TFTs increased as the applied tensile strain increased, but their electrical stability deteriorated under mechanical strain.

Enhancement of gate-bias and current stress stability of P-type SnO thin-film transistors with SiN x /HfO 2 passivation layers

In this letter, we report enhanced gate-bias and current stress stability of p-type SnO thin-film transistors passivated with SiNx/HfO2 layers. The improvement is primarily attributed to the effective suppression of bias-induced adsorption of oxygen molecules on the back-channel surface by the presence of passivation layers. Under the gate-bias stress of 10 V and -10 V for 10000 s, the threshold voltage shifts for the passivated TFT are 0.75 V and -0.42 V respectively, while the corresponding values for the unpassivated one are 1.24 V and -0.77 V Under the current stress of 2.5 μA for 10000 s, the threshold voltage shift is -0.29 V for the passivated TFT and -0.63 V for the unpassivated one.