I-Hsin Wang

A 0.18-

A 1.25-Gbps automatic-gain-control (AGC) amplifier is presented and it has been fabricated in 0.18-mum CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 dB from -10 to 18.5 dB, and its measured group delay is about 12.15 ns. For the bit-error rate of 10-12, the sensitivity and the overload for this AGC amplifier are 25 and 430 mV, respectively. It achieves input dynamic range of 24.7 dB. The power dissipation is 43.2 mW from a single 1.8-V supply voltage. The chip area is 0.82 mm times 0.56 mm includes I/O pads.

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This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistors sizes for the cascaded stages are inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for measurements. This chip has been fabricated in 0.13-mum 1P8M CMOS process and the total power consumption is 113 mW with IV supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200 MHz at 5-GSample/sec.

CMOS 1.25-Gbps Automatic-Gain-Control Amplifier

An 8-bit 20-MS/s time-domain analog-to-digital data converter (ADC) using the zero-crossing-based circuit technique is presented. Compared with the conventional ADCs, signal processing is executed in both the voltage and time domains. Since no high-gain operational amplifier is needed, this time-domain ADC works well in a low supply voltage. The proposed ADC has been fabricated in a 0.18-mum CMOS process. Its power dissipation is 4.64 mW from a supply voltage of 1.8 V. This active area occupies 1.2 times 0.7 mm2. The measured signal-to-noise-distortion ratio achieves 44.2 dB at an input frequency of 10 MHz. The integral nonlinearity is less than plusmn1.07 LSB, and the differential nonlinearity is less than plusmn0.72 LSB. This time-domain ADC achieves the effective bits of 7.1 for a Nyquist input frequency at 20 MS/s.

A 1V 5-Bit 5GSample/sec CMOS ADC for UWB Receivers

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in 0.13㎛ 1P8M CMOS process and the total power consumption is 113㎽ with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200㎒ at 5-GSample/sec.

An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter

A four-bit 10 GSample/sec flash analog-to-digital converter (ADC) with merged interpolation and reference voltage is presented. In this flash ADC, two clock-gated interpolation amplifiers are adopted and the number of resistor strings is reduced. An on-chip phase-locked loop is integrated to double sample the input signal and down sample the converted digital outputs, respectively. Furthermore, a digital-to-analog converter is embedded for the sake of measurements. This chip has been fabricated in 0.13 mum CMOS process and the ADCpsilas power consumption is 115 mW for a 1.2 V supply voltage. This ADC achieves the SNDR of 25 dB, INL of plusmn0.25 LSB, and DNL of plusmn0.5 LSB.

A CMOS 5-bit 5GSample/Sec Analog-to-digital Converter in 0.13um CMOS

A 5Gbps automatic gain control amplifier is presented with 27.8dB input dynamic range for 10GBase-LX4 Ethernet in 0.18mum CMOS technology. Five push-pull inverters use self-bias resistors and inductive-series peaking technique to realize a variable gain amplifier (VGA). This VGA achieves 4GHz bandwidth and 20dB linear-in-dB gain tuning range. The proposed 5Gbps AGC amplifier yields constant output amplitude 100mV for an input 27.8dB dynamic range

A 4-bit 10GSample/sec flash ADC with merged interpolation and reference voltage

A 7-bit 400 MS/s sub-ranging flash analog-to-digital data converter (ADC) with short latency is presented. To improve the sampling rate, the fine pre-amplifiers combined with the switched current sources are adopted instead of the switch matrix in a conventional sub-ranging ADC. The proposed architecture avoids the noise coupling from the switches and reduces the parasitic capacitances, which limit the resolution and bandwidth of a sub-ranging ADC. This prototype has been fabricated in 0.18um CMOS process. It dissipates 108 mW with a supply of 1.8 V and occupies the active area 0.64mm2. The measured performance achieves the signal to noise plus distortion ratio (SNDR) of 40 dB at sampling rate of 400 MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.9-LSB and ±0.7-LSB, respectively.

A 5Gbps CMOS Automatic Gain Control Amplifier for 10GBase-LX

A 5Gbps automatic gain control amplifier is presented with 27.8dB input dynamic range for 10GBase-LX4 Ethernet in 0.18mum CMOS technology. Five push-pull inverters use self-bias resistors and inductive-series peaking technique to realize a variable gain amplifier (VGA). This VGA achieves 4GHz bandwidth and 20dB linear-in-dB gain tuning range. The proposed 5Gbps AGC amplifier yields constant output amplitude 100mV for an input 27.8dB dynamic range

A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS

This paper presents the design and implementation of a 5Gb/s transimpedance amplifier (TIA) with dual shunt-shunt feedback technique to enhance the circuit performance. Measured bandwidth is 4.9GHz and measured transimpedance gain is 60 dB /spl Omega/. The chip consumes only 8mW at 1.8V supply voltage and occupies 650 /spl mu/m /spl times/ 500 /spl mu/m in a 0.18 /spl mu/m CMOS process.

10GBase-LX CMOS Automatic Gain Control Amplifier Design

An integrating analog-to-digital data converter (ADC) with variable resolution for radio-controlled servo motor applications is presented. A voltage-to-pulse converter VPC by using a pulse-controlled circuit is presented against the process variations. This integrating ADC is fabricated in a 0.18µm CMOS process and its resolution bit is reconfigurable from six to ten bits with the sampling rate from 4MSamples/sec to 250kSamples/sec.