I-Ru Chen

Substrate hole current and oxide breakdown

It is known that when an n‐channel metal‐oxide‐semiconductor field‐effect transistor is biased with a high positive gate voltage, a hole current appears in the substrate cathode. Recent experiments indicate that the holes are generated within the oxide. We show that this hole generation mechanism is linked to oxide time‐dependent breakdown. When the hole fluence reaches a certain critical value, breakdown occurs. This is in agreement with a hole‐trapping‐induced breakdown model. For very thin oxides the hole generation rate can become so low that the substrate hole current is dominated by the tunneling of valence‐band electrons which is not expected to contribute to oxide breakdown. A different mechanism of hole generation such as hot‐hole tunneling from the anode may be responsible for oxide breakdown in the important case of low gate voltage (<6 V).

Electron‐trap generation by recombination of electrons and holes in SiO2

It is shown that after holes are injected and trapped in silicon dioxide (SiO2), subsequent electron injection will generate neutral electron traps. The density of electron traps generated is about 30% of the density of trapped holes. It is proposed that electron traps are created by the energy released through the recombination of electrons and holes, and that this is the mechanism of electron‐trap generation during high‐field oxide stressing. Similar oxide field and thickness dependencies of the rate of electron‐trap generation and hole generation further support this model. This model can reconcile the main evidence for the electron‐trapping oxide breakdown model with the hole‐trapping breakdown model. It is consistent with the higher trap generation rate in irradiated SiO2. An analytical trapping model is derived and the electron capture cross sections of trapped holes and the generated neutral traps are found to be 10−14 cm2 and 5×10−16 cm2, respectively.

On physical models for gate oxide breakdown

Electrical breakdown of thin (32-nm) SiO2films subjected to constant-current stressing is studied. By studying the effects of reversing the polarity of the constant-current bias and the effects of thermal annealing on the charge-to-breakdown it is determined that electrical breakdown of SiO2is not caused by the widely-cited accumulation of trapped electrons. Rather it is caused by the buildup of positive charges near the cathode at localized areas. The positive charges are not mobile ions but exhibit many characteristics of trapped holes. We conclude that electrical breakdown in SiO2is caused by the accumulation of holes, generated by impact ionization in the oxide.

Oxide breakdown dependence on thickness and hole current - enhanced reliability of ultra thin oxides

The link between hole generation/trapping and oxide breakdown is demonstrated by correlating oxide breakdown with the hole current generated in the oxide. Both exhibit the same oxide thickness and field dependences. Charge-to-breakdown (QBD), time-to-breakdown (tBD), and breakdown-field (EBD) increase dramatically as oxide thickness is reduced below 80 Å due to reduced rate of hole generation, which is modeled by an average electron energy analysis. Time-dependent-dielectric-breakdown (TDDB) tests show that, for as-grown oxide capacitors, defect densities may decrease with decreasing oxide thickness down to 60 Å.

Accelerated testing of time-dependent breakdown of SiO 2

Electric-field acceleration factor β is the slope of the<tex>\log (t_{BD})</tex>versus E<inf>ox</inf>curve, where t<inf>BD</inf>is the time to breakdown at oxide field E<inf>ox</inf>. We report that β is not a constant but proportional to<tex>E\min{ox}\max{-2}</tex>. This is the main cause of the wide divergence of β values reported in the literature. The reported oxide thickness dependence of β is believed to be a result of the higher electron trap densities in thicker oxides. Oxide lifetime extrapolation using<tex>\log (t_{BD})</tex>, or better,<tex>\log (Q_{BD})</tex>against<tex>1/E_{ox}</tex>plots is more accurate and has a theoretical basis. Highly accelerated oxide testing appears to be feasible especially for very thin oxides.

Dynamic stressing of thin oxides

The breakdown of thin oxides due to DC stressing and uni-polarity and bi-polarity dynamic stressing has been compared. For dynamic stressing, the total integrated charge-to-breakdown, Q<inf>BD</inf>, and the total stressed time-to-breakdown, t<inf>BD</inf>, depend on both the pulse width and duty cycle of the stressing voltage. Uni-polarity and bipolarity stressing produce similar results. In all cases, both Q<inf>BD</inf>and t<inf>BD</inf>of dynamic stressing are greater than those of DC stressing. For 0.1 ms pulses, Q<inf>BD</inf>and t<inf>BD</inf>are about four times larger than what DC stressing would predict. The main reason for the higher Q<inf>BD</inf>and t<inf>BD</inf>under dynamic stressing is reduced hole trapping at localized weak oxide areas. A transient hole generation and relaxation model is proposed to quantitatively explain the increase in Q<inf>BD</inf>for dynamic stressing.

Comparison between CVD and thermal oxide dielectric integrity

Low-pressure chemical vapor deposited (CVD) oxide and thermal oxide of identical thickness (360 A) are compared. CVD oxide exhibits much lower incidence of breakdown at the electric fields below 8 MV/cm, in agreement with the notion that the breakdown is largely due to the incorporation of impurities in the silicon substrate into the oxide during thermal oxidation. Furthermore, CVD oxide shows identical IV characteristics as thermal oxide and significantly lower rates of electron and hole trapping. Based on these results, CVD oxide may be an intriguing candidate for thin dielectric applications.

The effect of channel hot carrier stressing on gate oxide integrity in MOSFET

The correlation between channel hot carrier stressing and gate oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate oxide integrity even when other parameters (e.g., Delta V/sub T/ and Delta VI/sub D/) have become intolerably degraded. In the extreme cases of stressing at V/sub G/ approximately=V/sub T/ with measurable hole injection current, however, the oxide charge-to-breakdown decreases linearly with the amount of hole fluence injected during the channel hot hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an electrostatic-discharge failure mechanism. >

Projecting the minimum acceptable oxide thickness for time-dependent dielectric breakdown

A technique is presented for determining the thinnest oxide which satisfies a given time-dependent dielectric breakdown reliability specification. The intrinsic limit for a 10-yr lifetime at 125 degrees C is estimated to be 80 A for 5.5-V operation and 50 A for 3.6-V operation. For the particular technology studies here, 150-AA oxide meets typical reliability specifications for 5.5-V operation, and 80-AA oxide is acceptable for 3.6-V operation (both at 125 degrees C).<<ETX>>

Hybrid CMOS/BEOL-NEMS technology for ultra-low-power IC applications

Three-dimensional (3-D) nano-electro-mechanical (NEM) switches (relays) are proposed to reduce the die area and power consumption of digital logic and memory circuits.