Louis Hutin

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/¿m at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~5 × 105), even at Lg = 55 nm.

Engineered substrates for future More Moore and More than Moore integrated devices

In 1991, M. Bruel (1) invented and patented the Smart Cut technology to fabricate Silicon On Insulator (SOI) substrates. The process relies on the transfer of a high quality single crystal layer from one wafer to another: implantation of gaseous ions in a single crystal wafer, direct bonding on a stiffener and splitting (Fig 1). The invention of this SOI process combined with the entrepreneurship of SOITEC paved the way to high quality SOI substrates mass production. Today, SOI is a mature product (up to 300mm diameter) and now developments are focused on the integration of new materials and functionalities in order to improve device performances and enlarge the application spectrum.

Characterization of Contact Resistance Stability in MEM Relays With Tungsten Electrodes

The impact of device operating parameters on the ON-state resistance (RON) of microelectromechanical relays with tungsten (W) electrodes is reported. Due to the susceptibility of W to oxidation, RON increases undesirably over the device operating cycles. This issue is aggravated by Joule heating when the relay is in the on state. The experimental results confirm that shorter ON time, as well as shorter off time, provides for more stable RON with respect to the number of ON/OFF switching cycles.

20nm gate length trigate pFETs on strained SGOI for high performance CMOS

We present the shortest and narrowest high-κ/metal gate n- and pFETs on compressively strained enriched SiGe On Insulator (c-SGOI) reported to date (L<inf>G</inf>=20nm; W=30nm; T<inf>SiGe</inf>=15nm). The range of active area widths in this work allows observing the transition from biaxial to uniaxial stress due to lateral elastic strain relaxation, and its benefit down to 20nm gate length on hole mobility and pFET performance (up to ×2.85 I<inf>Dlin</inf> enhancement vs. SOI, I<inf>ON</inf>=520µA/µm / I<inf>OFF</inf>=130nA/µm at L<inf>G</inf>=20nm and V<inf>DS</inf>=−1V). Moreover, an improved electrostatic integrity compared to SOI pFETs is demonstrated in c-SGOI (DIBL=120mV/V vs. 160mV/V, respectively at L<inf>G</inf>=30nm). Combined to the intrinsic |V<inf>th,p</inf>| lowering properties of c-SiGe, these characteristics qualify trigate c-SGOI as a very promising candidate for high performance pMOSFETs.

Hybrid CMOS/BEOL-NEMS technology for ultra-low-power IC applications

Three-dimensional (3-D) nano-electro-mechanical (NEM) switches (relays) are proposed to reduce the die area and power consumption of digital logic and memory circuits.

Adhesive Force Characterization for MEM Logic Relays With Sub-Micron Contacting Regions

Contact adhesive force (Fa) scaling is critical for relay miniaturization, since the actuation area and/or actuation voltage must be sufficiently large to overcome the spring restoring force (Fk) in order to turn on the relay and Fk must be larger than Fa in order to turn off the relay. In this work, contact adhesive force is investigated in MEM logic relays with contact dimple regions as small as 100 nm in lateral dimension. The results indicate that van der Waals force is predominant. An adhesive force of 0.02 nN/nm2 is extracted for tungsten-to-tungsten contact. Fa reduction should be possible with contact dimple size reduction and contact surface coating.

Boron and Phosphorus dopant activation in Germanium using laser annealing with and without preamorphization implant

In this work, we studied Excimer Laser Annealing at 308 nm with 180 ns pulse duration on Phosphorus and Boron implanted in Germanium, with or without Pre-Amorphization Implant (PAI) and co-implant. Using an industrial tool, experimental results show that we can achieve electrical activation levels up to 1.2×1020 cm−3 for P implant in Ge, which is the highest level regarding the appropriate mobility model. With the B implanted samples, we obtained an electrical activation level higher than 1×1020 cm−3 which is the better results obtained whithout PAI [1]. Melt thresholds were determined to be 0.65 J/cm² in amorphized Germanium (a-Ge) and 0.95 J/cm² in crystalline Germanium (c-Ge). With P, the best activation was obtained after a complete melt of the amorphous layer and the amorphous / crystalline (a/c) interface, necessary to obtain a perfectly recrystallized layer. In the case of B, we found a better activation in the submelt regime compared the melt one, and no contribution on the electrical activation with PAI was observed.

Experimental Investigation of Hole Transport in Strained

This paper presents a wide experimental study of hole transport in SiGe pMOSFETs. Various Ge contents, from 20% up to 60%, and growth templates [unstrained or tensely strained silicon-on-insulator (SOI)] were screened in order to study the influence of various strain levels and Ge concentrations. Electrical results have been compared with the amount of strain in the channel, characterized through dark-field electron holography and nano-beam electron diffraction. The SiGe channel/oxide interface has been investigated through spectroscopic charge pumping and low temperature measurements. We found the signature of Ge-induced defects, particularly near the valence band. The different scattering mechanisms limiting the hole mobility in long-channel transistors have been decorrelated and discussed in the light of the different experimental data provided. We have shown in particular the low contribution of alloy scattering in the SiGe devices under study, and that carrier transport is dominated by the strain effect for Ge content up to 40%. The roughness parameters of the SiGe channel/oxide interface are also modified, with a less prejudicial impact on mobility. The effect of strain and Ge content on the different scattering mechanisms has been established. The combination of all the scattering contributions leads to a maximum mobility at room temperature for a Ge content xGe = 0.4 on an SOI template, or equivalently, xGe = 0.6 on a strained SOI template.

\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{SOI}

The problematics of contacts optimization on germanium metal-oxide-semiconductor field-effect transistors suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals on Ge were so far mostly investigated on weakly n-doped samples under the pure thermionic emission regime. These experimental conditions are suitable for an accurate extraction; the measured Schottky barrier height (SBH) being usually large and linked to the interfacial current density by a relatively simple Arrhenius relationship. However, a device-oriented approach would consist in meeting the contact resistivity requirements in the ohmic regime for metallic contacts on a highly doped semiconductor (e.g., doped source and drain) through the choice of metal, interface preparation, and doping conditions. We hereby detail SBH extractions based on contact resistance (R co ) measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully processed germanium-on-insulator (GeOI) samples with Ti-based contacts, yielding effective barriers of 0.32 eV for electrons and 0.15 eV for holes. The method provides a good physical understanding of the technological factors impacting the electrical properties, enabling to define paths toward ohmic-contact optimization in the context of device integration on GeOI.

pMOSFETs—Part I: Scattering Mechanisms in Long-Channel Devices

Multiple-input relays are proposed to enable more compact implementation of digital logic circuits, and the first functional prototypes are presented. A relay with three equally sized input electrodes is demonstrated to perform various three-input logic functions, with a delay that can be well predicted by a lumped-parameter model. Relays with differently sized input electrodes can be used to perform more complex functions. A flash-type analog-to-digital converter is presented as one example.