I. Z. Mitrovic

Gd silicate: A High-k Dielectric Compatible with High Temperature Annealing

The authors report on the investigation of amorphous Gd-based silicates as high- k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd2 O3) and silicon oxide (Si O2) on silicon substrates are compared after annealing at temperatures up to 1000 °C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the Si O2 layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high- k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.

Leakage current effects on C-V plots of high-k metal-oxide-semiconductor capacitors

With the employment of ultrathin, high dielectric constant gate materials in advanced semiconductor technology, the conventional capacitance-voltage measurement technique exhibits a series of anomalies. In particular, a nonsaturating increase in the accumulation capacitance with reducing measurement frequency is frequently observed, which has not been adequately explained to our knowledge. In this article, the authors provide an explanation for this anomaly and hence set a criterion for the lower bound on measurement frequency. We then present a model which allows the easy extraction of the required parameters and apply it to an experimental set of data.

Compositional tuning of atomic layer deposited MgZnO for thin film transistors

Thin film transistors (TFTs) have been fabricated using magnesium zinc oxide (MgZnO) layers deposited by atomic layer deposition at 200 °C. The composition of the MgZnO is systematically modified by varying the ratio of MgO and ZnO deposition cycles. A blue-shift of the near band-edge photoluminescence after post-deposition annealing at 300 °C indicates significant activation of the Mg dopant. A 7:1 ratio of ZnO:MgO deposition cycles was used to fabricate a device with a TFT channel width of 2000 μm and a channel length of 60 μm. This transistor yielded an effective saturation mobility of 4 cm2/V s and a threshold voltage of 7.1 V, respectively. The on/off ratio was 1.6×106 and the maximum interface state density at the ZnO/SiO2 interface is ∼6.5×1012 cm−2.

'Ge interface engineering using ultra-thin La2O3 and Y2O3 films: A study into the effect of deposition temperature'

A study into the optimal deposition temperature for ultra-thin La2O3/Ge and Y2O3/Ge gate stacks has been conducted in this paper with the aim to tailor the interfacial layer for effective passivation of the Ge interface. A detailed comparison between the two lanthanide oxides (La2O3 and Y2O3) in terms of band line-up, interfacial features, and reactivity to Ge using medium energy ion scattering, vacuum ultra-violet variable angle spectroscopic ellipsometry (VUV-VASE), X-ray photoelectron spectroscopy, and X-ray diffraction is shown. La2O3 has been found to be more reactive to Ge than Y2O3, forming LaGeOx and a Ge sub-oxide at the interface for all deposition temperature studied, in the range from 44 °C to 400 °C. In contrast, Y2O3/Ge deposited at 400 °C allows for an ultra-thin GeO2 layer at the interface, which can be eliminated during annealing at temperatures higher than 525 °C leaving a pristine YGeOx/Ge interface. The Y2O3/Ge gate stack deposited at lower temperature shows a sub-band gap absorption f...

Breakdown and degradation of ultrathin Hf-based (HfO2)x (SiO2)1-x gate oxide films

Ultrathin films of hafnium oxide (HfO2) and hafnium silicate (HfO2)x(SiO2)1−x gate stacks (∼3nm) have been subjected to localized electrical stress with a conductive atomic force microscope (C-AFM) in ultrahigh vacuum. The nanoscale current-voltage (I-V) characteristics, prebreakdown temperature dependent I-V measurements on large area metal-insulator-semiconductor capacitors, postbreakdown (BD) topography, current maps, and AFM tip-surface contact force are used to interpret the progressive degradation of the oxide under electrical stress. For the pre-BD phase, trap-assisted tunneling and Fowler–Nordheim tunneling were found to be dominant current transport mechanisms in Hf-based gate stacks contributing to oxide leakage current. For the post-BD phase, an overall effect of barrier limited tunneling current on the charge propagation is confirmed and related to post-BD conductivity features observed by constant voltage scanning. A critical trap density required to trigger a BD event of the ultrathin (HfO2)...

Tuneable electrical properties of hafnium aluminate gate dielectrics deposited by metal organic chemical vapour deposition.

Abstract Hafnium aluminate (HfAlO) high-k films deposited by Metal Organic Chemical Vapour Deposition (MOCVD) with various Al concentrations were investigated. The results of electrical measurements show the feasibility of adjusting the relative dielectric constant of the layers in a wide range (9–16), when the aluminium concentration varies between 4% and 38%. The minimum leakage current occurs for Al concentrations up to 9%. The thinner films show Poole–Frenkel-like conduction at low field and Fowler–Nordheim-like conduction at moderate/high field, even at higher concentrations of Al into the film, while thicker films show a higher hysteresis due to an increased number of slow trapping centres in the film.

Non-parabolicity and band gap re-normalisation in Si doped ZnO

A combinatorial methodology, developed for the rapid optimisation of sputtered transparent conducting oxides, was applied to Si doped ZnO. A wide range of compositions have been explored over a single sample to determine an optimum composition, with respect to the minimisation of resistivity, of x = 0.65% wt. SiO2. A fundamental investigation of the conduction band non-parabolicity yields values of me0=0.35m0 and C = 0.3 eV−1 for the conduction band minimum effective mass and the non-parabolicity factor, respectively. The variation of extracted band gap values with respect to dopant concentration provided an estimate of the magnitude of re-normalization effects. A model is proposed to describe the carrier transport behaviour for a degenerate polycrystalline semiconductor by accounting for the tunnelling of carriers through grain boundaries.

'On the nature of the interfacial layer in ultra-thin TiN/LaLuO3 gate stacks'

We present a detailed investigation on the nature of the interfacial layer (IL) in ultra-thin TiN/LaLuO3 (LLO) gate stacks, which is of importance to facilitate CMOS scaling. The molecular beam deposited LaLuO3 films are found to be amorphous by high-resolution transmission electron microscopy. A similar to 9 angstrom thick LaLuO3/interlayer transition observed by medium energy ion scattering correlates with the presence of a dual silicate/SiO2-like interfacial layer derived from the analysis of photoelectron line positions and electron energy loss spectra. A theoretical model is used for the dielectric transition in a bi-layer LaLuO3/IL structure, linking physical and electrical characterization data. The obtained leakage current of 10(-3) A/cm(2) at 1.5 V and equivalent oxide thickness of 0.75 nm for TiN/LaLuO3 gate stacks are adequate for scaling in the 14-12 nm node.

Reliability studies on Ta2O5 high-κ dielectric metal-insulator-metal capacitors prepared by wet anodization

The temperature dependence of leakage current for tantalum oxide metal-insulator-metal capacitors has been investigated over the temperature range 20–160 °C. The leakage current shows an increase with temperature and the conduction mechanism at medium to high electric fields is in agreement with the modified Poole–Frenkel model. The activation energy of the dominant deep trapping center in the oxide is calculated using this model. Constant voltage and constant current stress have been applied to the devices and the effect of stress conditions on leakage current, breakdown voltage, and high frequency capacitance-voltage have been investigated. Early oxide breakdown or time-dependent dielectric breakdown was observed during constant voltage and constant current stress, in which the former is a function of stress time and applied voltage or current. There is an increase in leakage current with time during the constant voltage stress, presumably due to generation of positive defect states. This is also appare...

CV measurements on LaLuO3 stack metal-oxide-semiconductor capacitor using a new three-pulse technique

A new three-pulse CV measurement technique has been developed to investigate the trapping and detrapping of negative and positive charges in SiO2/LaLuO3 gate dielectric stacks on p-type silicon. Two types of negative and positive trapped charges have been observed in these devices which are deemed to be related to electron and hole trapping, respectively. The technique has the advantage that trapping and detrapping of both types of charges can be measured independently. The concentrations of trapped charge types, their release times, and their relationship with measurement parameters such as pulse charging/discharging time and pulse amplitude have been investigated. A logarithmic universal relationship was found between the flat-band voltage shifts due to detrapping of positive charges with the discharging time.