P. Ashburn

An investigation of the thermal stability of the interfacial oxide in polycrystalline silicon emitter bipolar transistors by comparing device results with high‐resolution electron microscopy observations

A comparison is made between the results of high‐resolution electron microscope observations and the electrical characteristics of polycrystalline silicon emitter bipolar transistors. Devices are fabricated with and without a deliberately grown interfacial oxide layer, and the thermal stability of this oxide layer is investigated by carrying out a preanneal at temperatures between 800 and 1100 °C after polysilicon deposition, but prior to emitter implant and 900 °C drive‐in. The electron microscope observations show that the deliberately grown interfacial oxide is of uniform thickness ∼14 A, but breaks up when annealed at ∼950 °C and above, with ‘‘balling‐up’’ occurring at ∼1100 °C. This correlates with a transistor gain that decreases from ∼1400 to ∼40. The electron microscopy also shows that a thin interfacial oxide layer is present even when not deliberately grown. This oxide breaks up when annealed at ∼900 °C and above, with ‘‘balling‐up’’ occurring at ∼1000 °C. This correlates with a transistor gain ...

Polysilicon emitters for bipolar transistors: a review and re-evaluation of theory and experiment

A critical review is presented of the theories proposed in the literature to explain the current gain enhancement of polysilicon emitter bipolar transistors. From these theories a simplified analytical formulation is chosen which models the blocking properties of the interface, including tunneling through the interfacial oxide, reduced grain boundary mobility at the polysilicon/silicon interface, and the potential barrier created by segregated dopant, which can all give rise to an enhanced current gain. Also modeled are the mechanisms which limit the extent of any gain enhancement, such as recombination in the single-crystal emitter, in the bulk of the polysilicon, and at the polysilicon/silicon interface. This model is then applied in an original manner to a selection of experimental data in an effort to identify the dominant current gain mechanisms in polysilicon emitter transistors as a function of a given set of fabrication conditions. >

Comparison of experimental and theoretical results on polysilicon emitter bipolar transistors

Two types of polysilicon emitter transistors have been fabricated using identical processing except for the surface treatment prior to polysilicon deposition. The first type was given a dip etch in buffered hydrofluoric acid, which was intended to remove any interfacial oxide, while the second type was given an RCA clean, which was intended to grow an interfacial oxide of known thickness. Detailed electrical measurements have been made on these devices including the temperature dependence of the gain over a wide temperature range. The transistors given an RCA clean have gains approximately five times higher than those given an HF etch. In addition, the temperature dependence of the gain is different for the two types, with the HF devices exhibiting a much stronger dependence at high temperatures than the RCA devices. A detailed comparison is made with the theory and it is shown that the characteristics of the HF devices can largely be explained using a transport theory, while those of the RCA devices can be fully explained using a modified tunneling theory.

Carbon nanotubes in a photonic metamaterial

Hybridization of single-walled carbon nanotubes with plasmonic metamaterials leads to photonic media with an exceptionally strong ultrafast nonlinearity. This behavior is underpinned by strong coupling of the nanotube excitonic response to the weakly radiating Fano-type resonant plasmonic modes that can be tailored by metamaterial design.

SiGe Heterojunction Bipolar Transistors

The world-wide electronics market is estimated to reach 200 billion

Investigation of boron diffusion in polysilicon and its application to the design of p-n-p polysilicon emitter bipolar transistors with shallow emitter junctions

in the year 2000. CMOS digital circuits represent the largest share of this market with their low-power consumption and the possibility of dynamic memories. Silicon Bipolar Junction Transistors (BJTs) are used in about 20% of all integrated circuits, mostly high-speed and analogue applications. The trend of steadily increasing switching speeds and communication rates demands further improvement of the performance of BJTs. In addition, at present the considerable number of BiCMOS circuits, which combine the high-current drive capability of BJTs with the low-power CMOS, demonstrates new applications for bipolar transistors.

Thin film polycrystalline silicon nanowire biosensors.

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow ( >

Numerically Efficient Modeling of CNT Transistors With Ballistic and Nonballistic Effects for Circuit Simulation

Polysilicon nanowire biosensors have been fabricated using a top-down process and were used to determine the binding constant of two inflammatory biomarkers. A very low cost nanofabrication process was developed, based on simple and mature photolithography, thin film technology, and plasma etching, enabling an easy route to mass manufacture. Antibody-functionalized nanowire sensors were used to detect the proteins interleukin-8 (IL-8) and tumor necrosis factor-alpha (TNF-α) over a wide range of concentrations, demonstrating excellent sensitivity and selectivity, exemplified by a detection sensitivity of 10 fM in the presence of a 100,000-fold excess of a nontarget protein. Nanowire titration curves gave antibody-antigen dissociation constants in good agreement with low-salt enzyme-linked immunosorbent assays (ELISAs). This fabrication process produces high-quality nanowires that are suitable for low-cost mass production, providing a realistic route to the realization of disposable nanoelectronic point-of-care (PoC) devices.

The use of an interface anneal to control the base current and emitter resistance of p-n-p polysilicon emitter bipolar transistors

This paper presents an efficient carbon nanotube (CNT) transistor modeling technique that is based on cubic spline approximation of the nonequilibrium mobile charge density. The approximation facilitates the solution of the self-consistent voltage equation in a CNT so that calculation of the CNT drain-source current is accelerated by at least two orders of magnitude. A salient feature of the proposed technique is its ability to incorporate both ballistic and nonballistic transport effects without a significant computational cost. The proposed models have been extensively validated against reported CNT ballistic and nonballistic transport theories and experimental results.

Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors

The effects of an interface anneal on the electrical characteristics of p-n-p polysilicon-emitter bipolar transistors are reported. For devices with a deliberately grown interfacial oxide layer, an interface anneal at 1100 degrees C leads to a factor of 15 increase in base current, and a factor of 2.5 decrease in emitter resistance, compared with an unannealed control device. These results are compared with identical interface anneals performed on n-p-n devices, and it is shown that the increase in base current for p-n-p devices is considerably smaller than that for the n-p-n devices. This result is explained by the presence of fluorine in the p-n-p devices, which accelerates the breakup of the interfacial layer.<<ETX>>