Iain Bate

Architectural considerations in the certification of modular systems

Abstract Modular system architectures, such as integrated modular avionics (IMA) in the aerospace sector, offer potential benefits of improved flexibility in function allocation, reduced development costs and improved maintainability. However, they require a new certification approach. The traditional approach to certification is to prepare monolithic safety cases as bespoke developments for a specific system in a fixed configuration. However, this nullifies the benefits of flexibility and reduced rework claimed of IMA-based systems and will necessitate the development of new safety cases for all possible (current and future) configurations of the architecture. This paper discusses a modular approach to safety case construction, whereby the safety case is partitioned into separable arguments of safety corresponding with the components of the system architecture. Such an approach relies upon properties of the IMA system architecture (such as segregation and location independence) having been established. The paper describes how such properties can be assessed to show that they are met and trade-offs performed during architecture definition reusing information and techniques from the safety argument process.

Low-level analysis of a portable Java byte code WCET analysis framework

To support portability, worst-case execution time (WCET) analysis of Java byte code is performed at two levels - machine-independent program flow analysis at a higher level and machine-dependent timing analysis of individual program constructs at a lower level. This paper contributes a WCET analysis that computes worst-case execution frequencies of Java byte codes within the software being analysed and accounts for platform-dependent information, i.e. the processors pipeline. The main part of the approach is platform-independent; only a limited analysis is needed on a per-platform basis.

An Integrated Approach to Scheduling in Safety-Critical Embedded Control Systems

This paper describes an approach that has been developed over a number of years for the job of scheduling systems and providing evidence that timing requirements are met. The approach has been targeted at the safety-critical systems domain, and more specifically the development of control systems for jet engines. The work provides a usable computational model that supports the reuse of legacy systems. In addition, timing analysis has been developed that features low pessimism, low computational complexity and that is robust to change. The contributions of this paper are to show how standard timing analysis is often insufficient for real systems, presenting extensions to the standard analysis to give an integrated approach to verification, and providing a case study that demonstrates the appropriateness and benefits of the overall technique.

Incorporating Scenarios And Heuristics To Improve Flexibility In Real-Time Embedded Systems

Flexibility, the ability to adapt to change, is important for real-time systems. As in any type of system, changes arise from maintenance, enhancements and upgrades. These changes are only feasible if timing requirements imposed by the real-time nature of the system can still be met. A flexible design will allow tasks to be added without impinging on other tasks, causing them to miss deadlines. The design space for these systems consists of many configurations describing how tasks and messages are allocated to hardware and scheduled on a hardware platform. Heuristic search is a well recognised strategy for solving allocation and scheduling problems but most research is limited to finding any valid solution for a current set of requirements. The technique proposed here incorporates scenario based analysis into heuristic search strategies where the ability of a solution to meet a scenario is included as another heuristic for the changeability of a system. This allows future requirements to be taken into account when choosing a solution so that future changes can be accommodated with minimal alterations to the existing system.

A Statistical Response-Time Analysis of Real-Time Embedded Systems

Real-time embedded systems are becoming ever more complex. We are reaching the stage where even if static Response-Time Analysis (RTA) was feasible from a cost and technical perspective, the results of such an analysis are overly pessimistic. This makes them less useful to the practitioner. In addition, the temporal validation and verification of such systems in some applications, e.g., aeronautics, requires the probability of obtaining a worst-case response time larger than a given value in order to support dependable system functions. All these facts advocate moving toward statistical RTA, which instead of calculating absolute worst-case timing guarantees, computes a probabilistic worst-case response time estimate. The contribution of this paper is to present and evaluate such a statistical RTA technique which uses a black box view of the systems under analysis, by not requiring estimates of parameters such as worst-case execution times of tasks. Furthermore, our analysis is applicable to real systems that are complex, e.g., from a task dependencies perspective.

A new way about using statistical analysis of worst-case execution times

In this paper, we revisit the problem of using Extreme Value Theory (EVT) in the Worst-Case Execution Time (WCET) analysis of the programs running on a single processor. Our proposed statistical WCET analysis method consists of a novel sampling mechanism tackling with some problems that hindered the application of using EVT in the context, and a statistical inference about computation of a WCET estimate of the target program. To be specific, the presented sampling mechanism takes analysis samples from the target program based around end-to-end measurements. Next, the statistical inference using EVT together with other statistical techniques, analyzes such timing traces which contain the execution time data of the program, to compute a WCET estimate with a certain predictable probability of being exceeded.

Worst-case execution time analysis for dynamic branch predictors

Branch prediction mechanisms are becoming commonplace within modern microprocessors. For developers of real-time control systems, the mechanisms present predictability problems. The reasons are they increase the difficulty in analysing software for its worst-case execution time without introducing unmanageable pessimism and they increase the variability of the softwares execution times. In this paper, we improve upon existing branch prediction analysis by taking into account the semantic context of the branches in the source code in order to classify them as either being easy-to-predict or hard-to-predict. Based on this classification we provide a static analysis approach for bimodal and global-history branch prediction schemes. The analysis is applied to a previously published example with the benefit that a more detailed explanation of its results is obtained.

Putting fixed priority scheduling theory into engineering practice for safety critical applications

Describes the approach proposed by the York University Technology Centre for introducing fixed-priority scheduling into industrial safety-critical hard real-time systems. The work has been performed within the context of a class A (safety-critical) system as defined by civil aircraft software standard DO178B. Traditionally, class A systems have been scheduled by a cyclic executive. However, many such systems can be re-designed using a fixed-priority scheduler. This saves time and money, with no significant increase in risk. Also, significant technical benefits are apparent. This paper describes the timing requirements of the system, provides a potential scheduling approach (including appropriate timing analysis), and outlines an approach for gathering the necessary evidence for presentation to certification authorities.

An approach to task attribute assignment for uniprocessor systems

The purpose of this paper is to investigate the issues related to task attribute assignment on an individual processor. The majority of papers on fixed priority scheduling make the assumption that tasks have their attributes (deadline, period, offset and priority) pre-assigned. This makes priority assignment trivial. However in practice, the systems timing requirements are specified and it is expected that the task attributes are synthesised from these. This paper is to present work that has been developed to solve this problem.

Schedulability analysis of fixed priority real-time systems with offsets

For a number of years, work has been performed in collaboration with industry to establish improved techniques for achieving and proving the system timing constraints. The specific requirements encountered during the course of this work for both uniprocessor and distributed systems indicate a need for an efficient mechanism for handling the timing analysis of task sets which feature offsets. Little research has been performed on this subject. The paper describes a new technique tailored to a set of real world problems so that the results are effective and the complexity is manageable.