Ian G. Harris

Testing and diagnosis of interconnect faults in cluster-based FPGA architectures

As IC densities are increasing, cluster-based field programmable gate arrays (FPGA) architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-base architecture is one in which several logic blocks are grouped together into a coarse-grained logic block. While the high-density local interconnect often found within clusters serves to improve FPGA utilization, it also greatly complicates the FPGA interconnect testing problem. To address this issue, we have developed a hierarchical approach to define a set of FPGA configurations which enable interconnect fault detection and diagnosis. This technique enables the detection of bridging faults involving intracluster interconnect and extracluster interconnect. The hierarchical structure of a cluster-based tile is exploited to define intracluster configurations separately from extracluster configurations, thereby improving the efficiency of the configuration definition process. The cornerstone of this work is the concise expression of the detectability conditions of each fault and the distinguishability conditions of each fault pair. By guaranteeing that both intracluster and extracluster configurations have several test transparency properties, hierarchical fault detectability is ensured.

BIST-based delay path testing in FPGA architectures

The widespread use of field programmable gate arrays (FPGAs) as components in high-performance systems has increased the significance of path delay faults in FPGAs. We present a technique for FPGA path delay fault detection which integrates test insertion with the FPGA placement and routing stages to accomplish testing with low test application time. An accurate static timing analyzer is used to identify critical paths and built-in self-test (BIST) hardware is inserted using a placement and routing tool. Initial experimental results show that testing is accomplished with low test application time for several benchmark designs.

Diagnosis of interconnect faults in cluster-based FPGA architectures

Fault diagnosis has particular importance in the context of field programmable gate arrays (FPGAs) because faults can be avoided by reconfiguration at almost no real cost. Cluster-based FPGA architectures, in which several logic blocks are grouped together into a coarse-grained logic block, are rapidly becoming the architecture of choice for major FPGA manufacturers. The high density interconnect found within clusters greatly complicates the problem of FPGA diagnosis. We propose a technique for the testing and diagnosis of cluster-based FPGA architectures. We present a hierarchical approach to define a set of FPGA configurations in which each fault is detectable, and each fault pair is differentiable. The cornerstone of this work is the concise expression of the distinguishing conditions of each fault pair. Experimental results demonstrate that nearly 100% fault coverage and diagnostic resolution are achieved with a low number of test configurations.

Interconnect testing in cluster-based FPGA architectures

As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which several logic blocks are grouped together into a coarse-grained logic block. While the high density local interconnect often found within clusters serves to improve FPGA utilization, it also greatly complicates the FPGA interconnect testing problem. To address this issue, we have developed a hierarchical approach to define a set of FPGA configurations which enable interconnect faults to be detected. This technique enables the detection of bridging faults involving intra-cluster interconnect and extra-cluster interconnect. The hierarchical structure of a cluster-based tile is exploited to define intra-cluster configurations separately from extra-cluster configurations, thereby improving the efficiency of the configuration definition process. By guaranteeing that both intra-cluster and extra-cluster configurations have several test transparency properties, hierarchical fault detectability is ensured.

Fault models and test generation for hardware-software covalidation

Mixed hardware-software systems constitute a strong paradigm shift for system validation. The main barriers to overcome are finding the right fault models and optimizing the validation flow. This article presents a research summary of these issues.

Hardware-Assisted Detection of Malicious Software in Embedded Systems

One of the critical security threats to computer systems is the execution of malware or malicious software. Several intrusion detection systems have been proposed which perform detection analysis in the software using the audit files generated by the operating system. Software-based solutions to this problem are relatively slow, so these techniques can be used forensically, but not in real-time to stop an exploit before it has an opportunity to do damage. We present a technique to implement intrusion detection for secure embedded systems by detecting behavioral differences between the correct system and the malware. The system is implemented using FPGA logic to enable the detection process to be regularly updated to adapt to new malware and changing system behavior.

A data flow fault coverage metric for validation of behavioral HDL descriptions

Behavioral HDL descriptions are commonly used to capture the high-level functionality of a hardware circuit for simulation and synthesis. The manual process of creating a behavioral description is error prone, so significant effort must be made to verify the correctness of behavioral descriptions. Simulation-based validation and formal verification are both techniques used to verify correctness. We investigate validation because formal verification techniques are frequently intractable for large designs. The first step toward a behavioral validation technique is the development of a validation fault coverage metric which can be used to evaluate the likelihood of design defect detection with a given test sequence. We propose a validation fault coverage metric which is based on an analysis of the control data flow description associated with the behavior. The proposed metric identifies a subset of paths through the data flow which must be traversed during testing to detect faults. The proposed metric is a tractable compromise between the statement coverage metric which requires only that each statement be executed, and the path coverage metric which requires that all data flow paths be executed. Data flow paths are identified based on the relative code locations of definitions and uses of variables which may be assigned incorrectly due to a design error. We propose an efficient method to compute all data flow paths which must be traversed, and we generate coverage results for several benchmark VHDL circuits for comparison to other approaches.

Application of built in self-test for interconnect testing of FPGAs

Field Programmable Gate Arrays (FPGAs) are becoming more difficult to test due to their increasing complexity and density. Test methodologies for FPGAs consist of generating numerous configurations of programmable switches that connect wire segments to create signal flow paths. We have developed a system that takes an arbitrary FPGA interconnect network and automatically generates configurations for test. These configurations detect single stuck-at faults, pair-wise bridging faults and wire-open faults. We have modified the traditional FordFulkerson Max-Flow algorithm to enable the efficient definition of test configurations. The system also generates the bitstreams, programs the FPGA, and displays the result. We have tested a Xilinx Virtex XCV150 and have presented the number of configurations and the test time for the device.

An on-demand scatternet formation and multi-hop routing protocol for BLE-based wireless sensor networks

As new features are introduced into the Bluetooth core specification, the ability to use Bluetooth Low Energy (BLE) technology to construct a mobile ad-hoc network (MANET) becomes a reality. Key features included in Bluetooth Specification version 4.1 are the ability for a single node to be part of multiple piconets, and the ability for a node to act dual mode, as both a piconet master and slave. These features allow the possibility of multi-hop routing spanning multiple connected piconets. Although multi-hop routing is theoretically possible with version 4.1, no multi-hop routing algorithm has never been presented which exploits this possibility. In this paper we propose an approach to scatternet formation and multi-hop routing for networks using BLE version 4.1. We define procedures for device discovery, communication between piconets and forming multi-hop scatternet. Our approach has the following properties, 1) it can be used with existing Bluetooth hardware, 2) the protocol is fully distributed, so global connectivity information is not required for formation and routing, and 3) it supports ad-hoc network formation. We have implemented our approach using real Bluetooth SoCs including the Broadcom BCM434x chipset which is used in the iPhone 6. Our experiments demonstrate the routing delay and throughput using networks containing different numbers of nodes in order to demonstrate the impact of network size on performance. As the network size increases, our protocol does not incur a large delay and achieves better resource utilization.

Practical Design Verification

Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT).