Shireesh Verma

An efficient control-oriented coverage metric

Coverage metrics, which evaluate the ability of a test sequence to detect design faults, are essential to the validation process. A key source of difficulty in determining fault detection is that the control flow path traversed in the presence of a fault cannot be determined. Fault detection can only be accurately determined by exploring the set of all control flow paths, which may be traversed as a result of a fault. We present a coverage metric that determines the propagation of fault effects along all possible faulty control flow paths. The complexity of exploring multiple control flow paths is greatly alleviated by heuristically pruning infeasible control flow paths using the algorithm that we present. The proposed coverage metric provides high accuracy in designs that contain complex control flow. The results obtained are promising.

Automatic generation of functional coverage models from CTL

Functional coverage models which measure the sufficiency of test stimuli are essential to the verification process. A key source of difficulty in their deployment emanates from the manual and imprecise nature of their development process and the lack of a sound measure of their quality. A functional coverage model can be considered complete only if it accurately reflects the behavior of the Design under Verification (DUV) as described in the specification. We present a method to automatically generate coverage models from a formal CTL description of design properties. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design.

Impact of SoC power management techniques on verification and testing

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power is a primary design criterion for bulk of the semiconductor designs now and a key reason behind the shift towards multicore designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions

As an industrial practice, the functional coverage models are developed based on a high-level specification of the design under verification (DUV). However, in the course of implementation a designer makes specific choices which may not be reflected well in a functional coverage model developed entirely from a high-level specification. We present a method to automatically generate implementation-aware coverage models based on the static analysis of a HDL description of the DUV. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design

Error Detection Using Model Checking vs. Simulation

Design simulation and model checking are two alternative and complementary techniques for verifying hardware designs. This paper presents a comparison between the two techniques based on detection of design errors, performance, and memory use. We perform error detection experiments using model checking and simulation to detect errors injected into a verification benchmark suite. The results allow a quantitative comparison of simulation and model checking which can be used to understand weaknesses of both approaches

Power Management Design and Verification

Power consumption has become the key differentiating factor for many different types of semiconductor products. This has led to recent advances in power management techniques to address power consumption in these products. These include power management techniques such as power gating, adaptive voltage and frequency scaling, and active body-bias that leverage voltage as a handle to manage power consumption. We look into an overview of these techniques and the resulting new challenges facing the functional validation of a system-on-a-chip.

Panel: SoC power management implications on validation and testing

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

Evaluation of an efficient control-oriented coverage metric

Dynamic verification, the use of simulation to determine design correctness, is widely used due to its tractability for large designs. A serious limitation of dynamic techniques is the difficulty in determining whether or not a test sequence is sufficient to detect all likely design errors. Coverage metrics are used to address this problem by providing a set of goals to be achieved during the simulation process; if all coverage goals are satisfied then the test sequence is assumed to be complete. Many coverage metrics have been proposed but no effort has been made to identify a correlation between existing metrics and design quality. In this paper we present a technique to evaluate a coverage metric by examining its ability to ensure the detection of real design errors. We apply our evaluation technique to our control-oriented coverage metric to verify its ability to reveal design errors.

Improving feasible interactions among multiple processes

Hierarchical testing requires the verification of individual processes followed by the verification of the interactions among processes. The large number of potential interactions between processes must be managed in order to make the testing process tractable. Fortunately, many potential interactions are actually infeasible and should be ignored during the verification process. Data dependency between processes indicates the potential for a feasible interaction but absolute feasibility can only be determined by evaluating control-flow paths across interacting processes. We propose a method to identify feasible interactions for testing through static analysis combined with the use of a constraint satisfaction programming (CSP) solving engine.