Ian Gray

Architecting Time-Critical Big-Data Systems

Current infrastructures for developing big-data applications are able to process –via big-data analytics- huge amounts of data, using clusters of machines that collaborate to perform parallel computations. However, current infrastructures were not designed to work with the requirements of time-critical applications; they are more focused on general-purpose applications rather than time-critical ones. Addressing this issue from the perspective of the real-time systems community, this paper considers time-critical big-data. It deals with the definition of a time-critical big-data system from the point of view of requirements, analyzing the specific characteristics of some popular big-data applications. This analysis is complemented by the challenges stemmed from the infrastructures that support the applications, proposing an architecture and offering initial performance patterns that connect application costs with infrastructure performance.

MADES FP7 EU project: Effective high level SysML/MARTE methodology for real-time and embedded avionics systems

The paper presents the EU funded MADES FP7 project, that aims to develop an effective model driven methodology to evolve current practices for the development of real time embedded systems for avionics and surveillance industries. In MADES, we propose an effective SysML/MARTE language subset and have developed new tools and technologies that support high level design specifications, validation, simulation and automatic code generation, while integrating aspects such as component re-use. The paper first illustrates the MADES methodology by means of a car collision avoidance system case study, followed by the underlying MADES language design phases and tool set which enable verification and automatic code generation aspects, hence enabling implementation in execution platforms such as state of the art FPGAs.

Exposing non-standard architectures to embedded software using compile-time virtualisation

The architectures of embedded systems are often application-specific, containing multiple heterogenous cores, non-uniform memory, on-chip networks and custom hardware elements (e.g. DSP cores). Standard programming languages do not use these many of these features natively because they assume a traditional single processor and a single logical address space abstraction that hides these architectural details. This paper describes Compile-Time Virtualisation, a technique which uses a virtualisation layer to map software onto the target architecture whilst allowing the programmer to control the virtualisation mappings in order to effectively exploit custom architectures.

Model-Based Hardware Generation and Programming - The MADES Approach

This paper gives an overview of the model-based hardware generation and programming approach proposed within the MADES project. MADES aims to develop a model-driven development process for safety-critical, real-time embedded systems. MADES defines a systems modelling language based on subsets of MARTE and SysML that allows iterative refinement from high-level specification down to final implementation. The MADES project specifically focusses on three unique features which differentiate it from existing model-driven development frameworks. First, model transformations in the Epsilon modelling framework are used to move between system models and provide traceability. Second, the Zot verification tool is employed to allow early and frequent verification of the system being developed. Third, Compile-Time Virtualisation is used to automatically retarget architecturally-neutral software for execution on complex embedded architectures. This paper concentrates on MADESs approach to the specification of hardware and the way in which software is refactored by Compile-Time Virtualisation.

Targeting complex embedded architectures by combining the multicore communications API (mcapi) with compile-time virtualisation

Within the domain of embedded systems, hardware architectures are commonly characterised by application-specific heterogeneity. Systems may contain multiple dissimilar processing elements, non-standard memory architectures, and custom hardware elements. The programming of such systems is a considerable challenge, not only because of the need to exploit large degrees of parallelism but also because hardware architectures change from system to system. To solve this problem, this paper proposes the novel combination of a new industry standard for communication across multicore architectures (MCAPI), with a minimal-overhead technique for targeting complex architectures with standard programming languages (Compile-Time Virtualisation). The Multicore Association have proposed MCAPI as an industry standard for on-chip communications. MCAPI abstracts the on-chip physical communication to provide the application with logical point-to-point unidirectional channels between nodes (software thread, hardware core, etc.). Compile-Time Virtualisation is used to provide an extremely lightweight implementation of MCAPI, that supports a much wider range of architectures than its specification normally considers. Overall, this unique combination enhances programmability by abstracting on-chip communication whilst also exposing critical parts of the target architecture to the programming language.

Architecture-Awareness for Real-Time Big Data Systems

Existing programming models for distributed and cloud-based systems tend to abstract away from the architectures of individual target nodes, concentrating instead on higher-level issues of algorithm representation (MapReduce etc.). However, as programmers begin to tackle the issue of Big Data, increasing data volumes are forcing developers to reconsider this approach and to optimise their software heavily. JUNIPER is an EU-funded project which assists Big Data developers to create architecture-aware software in a way that is suitable for the target domain, and provides higher performance, portability, and real-time guarantees.

Explicit Java control of low-power heterogeneous parallel processing in the ToucHMore project

This paper describes an approach to deploying Java on low-power, low-memory, heterogeneous multi-core systems. A goal of the effort is to enable the use of such systems in applications that must comply with real-time constraints, some of which must satisfy external certification authorities, thus the work is based on Safety Critical Java [4]. The heterogeneous multi-core system-on-a-chip considered have specialized purpose processors that can perform particular computations quickly and with less energy consumption than general-purpose processors. In order to allow a high degree of parallelism, these systems use partitioned memories, as opposed to the uniform memory access model traditionally supported by symmetric multiprocessors and the Java memory model. The effort is a work in progress. Syntax and tool chains are being developed and experimentation with the technologies has begun. But the current results are considered preliminary as many planned features are not yet fully implemented and performance optimization has not yet been completed. Consistent with the style of multi-core development in standard edition Java, the software engineer is responsible for orchestrating the division of labor between coprocessors.

Challenges in software development for multicore System-on-Chip development

Multiprocessor Systems-on-Chip (MPSoC)-based platforms are becoming more common in the embedded domain. Such systems are a significant deviation from the homogeneous, uniprocessor architectures that have been traditionally employed by embedded designers, thereby making the software development process to effectively target the platform more challenging. Low-resource embedded systems rely on efficient implementations that are not well supported by traditional solutions based on architecture virtualisation or middleware. Within this paper we examine these challenges and discuss ways in which they can be mitigated. In particular, we focus on the contributions made by two recent approaches based on Model-Driven Engineering (MDE). We also discuss challenges for future research.

Integrating Java 8 Streams with The Real-Time Specification for Java

The paper investigates the use of the Java 8 stream processing facilities within the context of the Real-Time Specification for Java. Java 8 stream processing uses the Java 7 Fork/Join framework. We demonstrate that it is not possible, with the current framework, to supply a pool of real-time worker threads with which to perform stream evaluation. We show what changes would need to be made to the framework for it to be used in a real-time context. Our evaluation shows that without such changes, use of the current Java 8 stream processing faculties by real-time threads can result in significant priority inversions. We also consider what hooks the RTSJ would need to allow real-time Fork/Join pools to be generated without changes to the source code.

A MARTE subset to enable application-platform co-simulation and schedulability analysis of NoC-based embedded systems

MARTE has matured into a substantial industrially relevant profile that extends UML expressive power to support the specification and design of embedded systems. When supported by appropriate model transformation and code generation tools, MARTE forms an appropriate starting point for embedded system development. In this paper we propose a simpler yet less powerful subset of MARTE, targeted at multiprocessor systems and amenable to early analysis (including timing) of design alternatives before committing to a particular design for implementation. We use the proposed subset of MARTE constructs to generate abstract simulation and real-time schedulability analysis models, allowing both average and worst-case performance metrics to be considered when comparing multiple design alternatives.