Leandro Soares Indrusiak

End-to-End Schedulability Tests for Multiprocessor Embedded Systems based on Networks-on-Chip with Priority-Preemptive Arbitration

Simulation-based techniques can be used to evaluate whether a particular NoC-based platform configuration is able to meet the timing constraints of an application, but they can only evaluate a finite set of scenarios. In safety-critical applications with hard real-time constraints, this is clearly not sufficient because there is an expectation that the application should be schedulable on that platform in all possible scenarios. This paper presents a particular NoC-based multiprocessor architecture, as well as a number of analytical methods that can be derived from that architecture, aiming to allow designers to check, for a given platform configuration, whether all application tasks and communication messages always meet their hard real-time constraints in every possible scenario. Experiments are presented, showing the use of the proposed methods when evaluating different task mapping and platform topologies.

Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching

In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. The authors present a novel off-line schedulability analysis approach, worst case network latency analysis. By evaluating diverse inter-relationships and service attributes among the traffic flows, this approach can predict the packet network latency for all practical situations. The simulation results provide evidence that communication latency calculated using the real time analysis approach is safe, closely matching the figures obtained from simulation.

A Wormhole NoC Protocol for Mixed Criticality Systems

Lack of scalability and difficulties in predicting the temporal behaviour of bus-based architectures has lead to the development of Network-on-Chip (NoC) protocols that provide a schedulable resource for moving data across multi-core platforms. Wormhole switching and credit-based flow control protocols have been used to support flit-level priority-preemptive link arbitration in NoCs, which leads to analysable temporal behaviour. In this paper we develop a new protocol (WPMC), based on the same family of protocols, that gives full support to mixed-criticality on-chip communications. WPMC is defined to give adequate partitioning between criticality levels, and to use resources efficiently. Analysis is developed and implementation aspects are considered. A cycle accurate simulator is used for scenario-based verification, and the effectiveness of the protocol and its scheduling model is evaluated via message-set generation.

On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems

The design of digital electronic systems for industrial applications can benefit in many ways from the prototyping capabilities of field-programmable gate array (FPGA) platforms. This paper presents three evolutionary releases of an FPGA-based remote laboratory and discusses the didactical and technical motivations behind each release, aiming to reduce the overhead of setting up and operate a laboratory environment where designers and students can use FPGA prototyping to validate their designs. To achieve that, a number of abstraction layers were introduced, allowing configuration and data processing in remote FPGA platforms, as well as integrating such platforms within a simulation environment. The proposed approach supported a number of projects where groups of designers and students could specify, refine, and prototype electronic systems using a pool of remotely available FPGA platforms.

Real-time low-power task mapping in Networks-on-Chip

Many state-of-the-art approaches to power minimisation in Networks-on-Chip (NoC) are based on the reduction of the communication paths taken by packets over the interconnect. This is often done by optimising the packet routing, the allocation of tasks that produce and consume those packets, or both. In all cases, the optimisation affects the timeliness of the packets, because changes will occur in the way resources are shared at the platform cores (as tasks are reallocated) and NoC links (as packet routes are changed). In this paper, we propose an optimisation technique that is able to minimise power dissipation without sacrificing timing constraints, thus suitable to systems with hard real-time requirements. It is based on a Genetic Algorithm (GA) that evolves chromosomes representing the mapping of tasks to cores, guided by a multi-objective fitness function that combines power estimation macromodels and real-time schedulability analysis.

Using genetic algorithms to map hard real-time on NoC-based systems

This paper investigates the effectiveness of genetic algorithms (GAs) for static task scheduling in wormhole Network-on-Chip-based systems. The overall objective was to get the application model mapped onto the architecture so that all tasks and communication meet their deadlines. Inter-task communication is accounted for by using analytical methods. The GA explores both the mapping of tasks as well as the priority ordering of the task set. A novel fitness function was developed and found to perform better than existing functions.

Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach

The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the utilization of processors and interconnect can be taken into account when deciding the allocation of each task. This paper has two major contributions, one of them targeting the general problem of evaluating dynamic mapping heuristics in NoC-based MPSoCs, and another focusing on the specific problem of finding a task mapping that optimizes energy consumption in those architectures.

Genetic mapping of hard real-time applications onto NoC-based MPSoCs — A first approach

Despite its significance to embedded systems industry and research communities, little research has been done on providing guarantees for hard real-time applications running over multicore processors based on wormhole Networks-on-Chip (NoCs). This work takes advantage of recent work on schedulability analysis that is tailored to such platforms, and uses it as a ranking function in a genetic algorithm that is able to evolve task mappings which allow all tasks and communication flows to meet their deadlines in all possible scenarios.

Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration

Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on-chip interconnects through transaction-level modelling (TLM). A particular on-chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a way that accurate figures for communication latency can be obtained with less simulation time than a cycle-accurate model. The proposed model produced latency figures with more than 90% accuracy and simulated more than 1000 times faster than a cycle-accurate model.

Exploring NoC-Based MPSoC Design Space with Power Estimation Models

This model-based methodology and supporting toolset lets designers estimate application-specific network-on-chip (NoC) power dissipation at early stages of the design flow. An actor-oriented simulation framework captures the NoCs dynamic behavior and feeds its parameters to a rate-based power estimation model. Integrating this model into the proposed design flow enables the analysis of different design parameters and the identification of the most power-efficient application platform mappings.