Igone Velez

Radix

This paper proposes to use the discrete Fourier transform (DFT) matrix factorization based on the Kronecker product to express the family of radix <i>rk</i> single-path delay commutator/single-path delay feedback (SDC/SDF) pipeline fast Fourier transform (FFT) architectures. The matricial expressions of the radix <i>r</i>, <i>r</i> ², <i>r</i> ³, and <i>r</i> ⁴ decimation-in-frequency (DIF) SDC/SDF pipeline architectures are derived. These expressions can be written using a small set of operators, resulting in a compact representation of the algorithms. The derived expressions are general in terms of <i>r</i> and the number of points of the FFT <i>N</i>. Expressions are given where it is not necessary that <i>N</i> is a power of <i>rk</i>. The proposed set of operators can be mapped to equivalent hardware circuits. Thus, the designer can easily go from the matricial representations to their implementations and vice versa. As an example, the mapping of the operators is shown for radix 2, 2², 2³, and 2⁴, and the details of the corresponding SDC/SDF pipeline FFT architectures are presented. Furthermore, a general expression is given for the SDC/SDF radix <i>rk</i> pipeline architectures when <i>k</i> > 4. This general expression helps the designer to efficiently handle a wider design exploration space and select the optimum single-path architecture for a given value of <i>N</i>.

r^{k}

Computer vision technologies can contribute in many ways to the development of smart cities. In the case of vision applications for advanced driver assistance systems (ADAS), they can help to increase road traffic safety, which is a major concern nowadays. The design of an embedded vision system for driver assistance is not straightforward; several requirements must be addressed such as computational performance, cost, size, power consumption or time-to-market. This paper presents a novel reconfigurable embedded vision system that meets the requirements of ADAS applications. The developed PCB board contains a System on Chip composed of a programmable logic that supports parallel processing necessary for a fast pixel-level analysis, and a microprocessor suited for serial decision making. A lane departure warning system was implemented in the case study, obtaining a better computational performance than the rest of the works found in the literature. Moreover, thanks to the reconfiguration capability of the proposed system a more flexible and extensible solution is obtained.

FFTs: Matricial Representation and SDC/SDF Pipeline Implementation

A new methodology to teach digital hardware design with a limited time budget is presented. The emphasis is placed on training hardware engineers to answer the needs of the industry. The proposed course is focused on teaching how to design rather than just teaching a hardware description language or a set of tools. This goal is achieved through lectures, tutorials, and small projects. Projects are the core of the proposed methodology and are structured in a pedagogical format. The students must follow the entire design process in all the projects. They receive a written specification that they must interpret. The deliverables are a functionally verified code that meets some synthesis constraints and a report that documents their design. Histograms of the grades are used as a tool to study the students progress.

A reconfigurable embedded vision system for advanced driver assistance

This article presents an indoor localization system based on Impulse-Radio Ultra-Wideband. A novel peak detection technique is proposed to be used for Round-Trip-Time ranging. Additionally, the accuracy and complexity of different positioning algorithms are studied. The effect of different configurations of the fixed and mobile transceivers on the accuracy is also analyzed. Simulations have been performed using realistic multipath channel models and the parameters of the IEEE 802.15.4a standard. These simulations show that the proposed localization system is able to achieve enough accuracy for an ambient assisted living application in any of the analyzed configurations.

A Course to Train Digital Hardware Designers for Industry

This paper presents a new transaction level assertion verification framework built on top of SystemC to support the integration of Assertion Based Verification in a Model Driven Design methodology. A key point of the proposed framework is that it enables decoupling the work of the design and verification teams. This is possible thanks to data introspection capabilities; the fact that the assertions are not embedded in the design model code; and the abstraction in the property specification. Thus, the two teams can work in parallel starting from the natural language specification, reducing the development time.

Design of an IR-UWB Indoor Localization System Based on a Novel RTT Ranging Estimator

Design patterns and tools to describe the functionality of a system at a high abstraction level are presented. These design patterns allow the designers to easily go from UML use case and state diagrams to a SystemC executable model.

A Transaction Level Assertion Verification Framework in SystemC: An Application Study

This paper addresses the estimation and compensation of I/Q imbalance, one of the most prominent impairments found in wideband zero-intermediate frequency transceivers (TRxs). The I/Q imbalance encountered in this kind of TRx comprises not only frequency-selective gain and phase imbalance but also delay imbalance. Unless appropriate compensation is applied, the I/Q imbalance significantly degrades the performance of a communication system. This paper presents a novel compensation technique for transmitter I/Q imbalance based on built-in-self-calibration, a low cost and robust compensation technique that enables manufacturing as well as in-field calibration with low computational complexity. The method’s performance is evaluated in a TRx with 64-quadratic-amplitude modulation and 2 GHz of bandwidth implemented with real hardware. The measurements show that the proposed technique achieves an image rejection ratio greater than 35 dB in the entire 2 GHz bandwidth and an error vector magnitude lower than 3%.

System behaviour capture: from UML to SystemC

This paper considers the design of a parallel sample rate interpolation filter for the backhaul of the future mobile networks. These future networks must provide Gigabit data rates, which relay on the use of high spectral efficiency, high bandwidth baseband signals. Parallel signal processing becomes a necessity since state of the art technology is incapable of serially generating and converting these high bandwidth signals. Moreover, signal generation and digital-to-analog conversion are performed under incommensurate clock domains. Therefore, interpolation becomes a necessity when connecting signal generation to signal conversion. The paper analyses the interpolation equation and discusses several techniques to achieve a parallel implementation. The designed interpolation filter has been tested to adapt an incoming signal data stream at a rate of 1.7 giga-symbols per second into a stream of interpolants at a rate of 2.8 giga-interpolants per second under two incommensurate clock domains.

Built-in-Self-Calibration for I/Q Imbalance in Wideband Millimeter-Wave Gigabit Transmitters

In this paper we consider the problem of estimating the signal-to-noise ratio (SNR) of the received signal in a QPSK data transmission system. This estimation must be done in-service (non-data aided), without carrier phase knowledge and without symbol timing phase knowledge. New algorithms with these features are derived from the ratio of two moments. The performance of these algorithms is studied by means of simulations, and it is shown that they are robust against carrier and symbol timing frequency offsets as well. This makes them suitable for a wide range of applications.

Parallel implementation of a sample rate conversion and pulse-shaping filter for high speed backhauling networks

In this paper, image processing algorithms designed in Zynq SoC using the Vivado HLS tool are presented and compared with hand-coded designs. In Vivado HLS, the designer has the opportunity to employ libraries similar to OpenCV, a library that is well-known and wide used by software designers. The algorithms are compared in terms of area resources in two conditions: using the libraries and not using the libraries. The case studies are Data Binning, a Step Row Filter and a Sobel Filter. These algorithms have been selected because they are very common in the field of image processing and they have high computational complexity. The main benefit of the Vivado HLS tool is the reduction in time-to-market. On the other hand, when a software designer hand-codes the design, the use of image processing libraries similar to OpenCV helps to reduce development time even further because software designers are familiar with them. However, using these kinds of libraries significantly increases the necessary FPGA resources.