Juan F. Sevillano

Radix

This paper proposes to use the discrete Fourier transform (DFT) matrix factorization based on the Kronecker product to express the family of radix <i>rk</i> single-path delay commutator/single-path delay feedback (SDC/SDF) pipeline fast Fourier transform (FFT) architectures. The matricial expressions of the radix <i>r</i>, <i>r</i> ², <i>r</i> ³, and <i>r</i> ⁴ decimation-in-frequency (DIF) SDC/SDF pipeline architectures are derived. These expressions can be written using a small set of operators, resulting in a compact representation of the algorithms. The derived expressions are general in terms of <i>r</i> and the number of points of the FFT <i>N</i>. Expressions are given where it is not necessary that <i>N</i> is a power of <i>rk</i>. The proposed set of operators can be mapped to equivalent hardware circuits. Thus, the designer can easily go from the matricial representations to their implementations and vice versa. As an example, the mapping of the operators is shown for radix 2, 2², 2³, and 2⁴, and the details of the corresponding SDC/SDF pipeline FFT architectures are presented. Furthermore, a general expression is given for the SDC/SDF radix <i>rk</i> pipeline architectures when <i>k</i> > 4. This general expression helps the designer to efficiently handle a wider design exploration space and select the optimum single-path architecture for a given value of <i>N</i>.

r^{k}

A full passive UHF pressure RFID tag is presented in this work. Special attention is paid to the novel capacitive sensor-interface and the analog FE which were designed and implemented on a low cost 0.35µm standard CMOS technology. The characterization of the fabricated sensor interface connected to a pressure MEMS transducer shows a fully digital output with an ENOB of 7.27 bits and an FOM of 5.47pJ. The fabricated analog front-end, assembled to a matched dipole antenna, was connected to the digital core and the implemented pressure sensor. The RFID pressure sensor tag was characterized inside a PVC pressure chamber. Successful ID and pressure measurement (30kPa–120kPa) communication with a commercial RFID reader over a distance of 1.5m was achieved using the EPC Gen 2 standard. These characteristics allow the use of the proposed system in long range wireless pressure sensing and motivates the implementation of the proposed capacitive sensor interface in passive wireless sensors.

FFTs: Matricial Representation and SDC/SDF Pipeline Implementation

A new methodology to teach digital hardware design with a limited time budget is presented. The emphasis is placed on training hardware engineers to answer the needs of the industry. The proposed course is focused on teaching how to design rather than just teaching a hardware description language or a set of tools. This goal is achieved through lectures, tutorials, and small projects. Projects are the core of the proposed methodology and are structured in a pedagogical format. The students must follow the entire design process in all the projects. They receive a written specification that they must interpret. The deliverables are a functionally verified code that meets some synthesis constraints and a report that documents their design. Histograms of the grades are used as a tool to study the students progress.

A passive UHF RFID pressure sensor tag with a 7.27 bit and 5.47pJ capacitive sensor interface

This paper presents a new transaction level assertion verification framework built on top of SystemC to support the integration of Assertion Based Verification in a Model Driven Design methodology. A key point of the proposed framework is that it enables decoupling the work of the design and verification teams. This is possible thanks to data introspection capabilities; the fact that the assertions are not embedded in the design model code; and the abstraction in the property specification. Thus, the two teams can work in parallel starting from the natural language specification, reducing the development time.

A Course to Train Digital Hardware Designers for Industry

This paper presents a nonius-based time-to-digital converter (TDC) for its use as part of a RFID tag sensor. The TDC can digitize any physical magnitude previously converted to time delay and it exploits the benefits of time domain conversion: high resolution with reduced power consumption and low voltage operation. A high level study is carried out to analyze the feasibility of the nonius-based TDC for RFID sensing applications. A calibration strategy tailored for RFID sensing applications is proposed that makes the TDC very robust against process and mismatch variations. Subgate resolution is analyzed to overcome the technology gate delay limits. An implementation of the converter using a 0.18-µm CMOS standard process has been analyzed for human body temperature sensing applications. A resolution of 0.035°C and accuracy value of 0.053°C are achieved in the range from 35°C to 43°C. The average power consumption of the converter is only 3.9nW at 10 samples per second from a 1.8V voltage supply.

A Transaction Level Assertion Verification Framework in SystemC: An Application Study

Design patterns and tools to describe the functionality of a system at a high abstraction level are presented. These design patterns allow the designers to easily go from UML use case and state diagrams to a SystemC executable model.

Nonius based time-to-digital converter for low-power RFID sensory systems

This paper addresses the estimation and compensation of I/Q imbalance, one of the most prominent impairments found in wideband zero-intermediate frequency transceivers (TRxs). The I/Q imbalance encountered in this kind of TRx comprises not only frequency-selective gain and phase imbalance but also delay imbalance. Unless appropriate compensation is applied, the I/Q imbalance significantly degrades the performance of a communication system. This paper presents a novel compensation technique for transmitter I/Q imbalance based on built-in-self-calibration, a low cost and robust compensation technique that enables manufacturing as well as in-field calibration with low computational complexity. The method’s performance is evaluated in a TRx with 64-quadratic-amplitude modulation and 2 GHz of bandwidth implemented with real hardware. The measurements show that the proposed technique achieves an image rejection ratio greater than 35 dB in the entire 2 GHz bandwidth and an error vector magnitude lower than 3%.

System behaviour capture: from UML to SystemC

This paper considers the design of a parallel sample rate interpolation filter for the backhaul of the future mobile networks. These future networks must provide Gigabit data rates, which relay on the use of high spectral efficiency, high bandwidth baseband signals. Parallel signal processing becomes a necessity since state of the art technology is incapable of serially generating and converting these high bandwidth signals. Moreover, signal generation and digital-to-analog conversion are performed under incommensurate clock domains. Therefore, interpolation becomes a necessity when connecting signal generation to signal conversion. The paper analyses the interpolation equation and discusses several techniques to achieve a parallel implementation. The designed interpolation filter has been tested to adapt an incoming signal data stream at a rate of 1.7 giga-symbols per second into a stream of interpolants at a rate of 2.8 giga-interpolants per second under two incommensurate clock domains.

Built-in-Self-Calibration for I/Q Imbalance in Wideband Millimeter-Wave Gigabit Transmitters

This paper presents a comparative study on time-to-digital converters (TDC) for their use as part of an RFID tag sensor. TDCs can digitize any physical magnitude previously converted to time delay and exploit the benefits of time domain conversion: high resolution with reduced power consumption and low voltage operation. Three different TDC architectures are analyzed and a calibration strategy tailored for RFID sensing applications is proposed in order to account for process variations. Converters implemented using a 0.18@mm CMOS standard process have been analyzed at transistor level for human body temperature sensing applications. An accuracy of 0.011^oC is achieved in the range from 35^oC to 43^oC for the nonius TDC with a power consumption of only 4.1nW at 10 samples per second from a 1.8V voltage supply.

Parallel implementation of a sample rate conversion and pulse-shaping filter for high speed backhauling networks

In this paper we consider the problem of estimating the signal-to-noise ratio (SNR) of the received signal in a QPSK data transmission system. This estimation must be done in-service (non-data aided), without carrier phase knowledge and without symbol timing phase knowledge. New algorithms with these features are derived from the ratio of two moments. The performance of these algorithms is studied by means of simulations, and it is shown that they are robust against carrier and symbol timing frequency offsets as well. This makes them suitable for a wide range of applications.