Ikuo Tokizawa

Self-healing ATM networks based on virtual path concept

This paper proposes self-healing network techniques suitable for ATM networks in order to realize a high-reliablity B-ISDN. First, the characteristics of the virtual paths (VP) and their influence on failure restoration are discussed. A high-speed restoration technique which exploits the benefits of the VP is then proposed and described. The technique simplifies the message transmission processes and reduces the number of generated messages by using preassigned backup virtual paths. Next, the scheme used to design the backup VP routes and spare resource distribution for each link is proposed in order to create a network that applies the proposed restoration scheme. Next, self-reconstruction techniques of backup virtual paths are proposed for the realization of a reversionless restoration cycle. Finally, the feasibility of the distributed control operation is discussed. >

Implementation of self-healing function in ATM networks based on virtual path concept

This paper proposes an implementation scheme for the self-healing function in ATM networks and assesses its performance. First, our proposed ATM self-healing scheme is described. This scheme realizes more rapid restoration of failed virtual paths than other self-healing algorithms, supports the node failure case, and minimizes the spare resources required. Next, an implementation scheme is proposed. We propose that the self-healing function be implemented as a software process, and that OAM cells are utilized for fast message transmission. Next, results of a prototype system that we implemented on an ATM cross-connect system are discussed. The fundamental characteristics of restoration performance are measured using an experimental network. Based on these results, an NE processing system analysis and computer simulation for estimating the characteristics as applied to a real-scale network are discussed. Finally, a management scheme for self-healing is proposed based on the TMN concept.

ATM transport system architecture and field trial

The ATM link system will play an important role in constructing virtual path transport networks for the future B-ISDN. A prototype ATM link system is implemented that exhibits the benefits of ATM to the greatest possible extent. This system features not only very high-speed line interfaces, large capacity cross-connect networks, and built-in functions that contribute to efficient operation and maintenance, but also very compact equipment using state-of-the-art technologies. The paper describes the B-ISDN network architecture, ATM link system role in the networks, newly developed technologies, and the implemented system.<<ETX>>

Direct virtual path configuration in large-scale ATM networks

The paper presents a new ATM transport network technique that realizes the direct virtual path configuration by using path bandwidth control and the virtual path group concept. Direct virtual paths link local switches directly and enable channel set up processing to be eliminated from transit nodes. However, this configuration, which employs no toll switches, suffers from several problems such as reduced utilization of virtual path bandwidth and increased difficulty of localized network management based on network segmentation. The authors introduce virtual path bandwidth control and the virtual path group concept into ATM transport networks to realize the direct virtual path configuration in a very efficient manner. Virtual path bandwidth control enables the optimum balance between switching and transmission systems to be struck. Virtual path groups make it possible to provide a localized network management capability in a way similar to that available in a conventional network.<<ETX>>

Evaluation of an Experimental Packetized Speech and Data Transmission System

The design objectives and test results of a new services integrated system using a packetized speech technique are presented. First, several important design parameters are investigated through theoretical analysis and computer simulation. Second, an experimental system for confirming the choice of design parameters as well as measuring the speech and data communication quality is described, and the test results of this system are discussed.

Implementation of self-healing function in ATM networks

This paper proposes an implementation scheme for the self-healing function in ATM (Asynchronous Transfer Mode) networks and assesses its performance in a developed experimental system. First, our proposed ATM self-healing scheme is described. This scheme realizes more rapid restoration of failed Virtual Paths than other self-healing algorithms, supports the node failure case, and minimizes the spare resources required. Next, an implementation scheme is proposed. We propose that the self-healing function can be implemented as a software process, and that OAM (Operation, Administration, and Maintenance) cells be utilized for fast message transmission. Next, results of a prototype system that we implemented on an ATM cross-connect system are discussed. The fundamental characteristics of restoration performance are measured using the experimental system. Based on these results, restoration characteristics of real world scale networks are estimated by computer simulations. The simulation results indicate that any-one link failure is completely restored within 2 seconds.

A Synchronous DS4 Multiplexer with Cross-Connect Function

The development and system design of a new synchronous DS4 multiplexer with cross-connect function is described. This new multiplexer is expected to provide cost reductions due to more efficient use of transmission facilities, and rapid circuit provisioning. The multiplexer consists of three kinds of digital cross-connect blocks, a transmission terminating block, an intraoffice-interface block, and a controler. It is also expected to provide improved network maintenance, higher network reliability, and greater system versatility for new services.

SDH line-error detection method using reduced BIP

For STM-N transmission lines in a synchronous digital hierarchy (SDH), a 24N bits interleaved parity (BIP) detection code is established in order to monitor transmission line errors. the hardware required for BIP code calculation increases in proportion to the speed of the transmission line. For example, with STM-16 (2.48832 Gbit/s), the BIP code uses 384 bits, and the line-error detection function occupies a large portion of the SDH interface hardware. This paper proposes a method to solve the foregoing problem, which implements line-error detection by using a shorter BIP code obtained by conversion of the received BIP code, at the receiving end. At the transmitting end, BIP code conforming with the ITU-T (formerly CCITT) standard is generated. This method allows integration with international standards, without degrading performance. That is, with an STM-16, the hardware size is reduced by about 3000 gates, which is approximately a 20 percent reduction in the total gate count of an SDH processor.