Il-gon Kim

21.4: Development of SLS-Based System on Glass Display

2-inch qVGA (240×320) TFT-LCD with integrated 6-bit source driver is reported. TS-SLS (Two-Shot Sequential Lateral Solidification) technique has been employed to improve the TFT characteristics. Thanks to the superb characteristics of the TS-SLS TFTs, 1:6 de-multiplexing driving scheme has been successfully implemented in the source driver, which resulted very compact circuit area and the highest resolution (200ppi) SOG (System on Glass) display ever reported.

Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices

Radiation-induced Soft Error Rate (SER) of SRAM built in 14nm FinFET on bulk technology was extensively characterized. Two different SRAM cells, high-performance (HP) and high-density (HD), were irradiated with alpha particles, thermal neutrons, and high-energy neutrons. Empirical results reveal excellent SER performance of FinFET compared to the prior technology nodes, drastically reducing SER FIT rate by 5-10X. It is found that HP cell is more sensitive to a single event upset than HD cell design. We will discuss the effects of charge collection efficiency as one of major parameter and present supporting simulation results.

A 7‐inch Full‐Color Low‐Temperature Poly‐Si TFT‐LCD

A 7-inch full-color low-temperature poly-Si TFT-LCD with fully integrated driver circuits has been developed. Employing a novel LDD structure in the CMOS integrated drivers, highly stable devices have been attained. It was designed to provide various types of images, such as full, cinema, normal, and wide mode. The 7-inch TFTLCD is applicable for the car-navigation system or PDA applications.

P‐3: Panel Transmittance Analysis of PVA Mode and a Noble Pixel Design

Vertical Alignment mode TFT-LCD is divided into MVA mode through formation of protrusion, PVA mode that uses color filter ITO patterning and etc. Among these, R&D of PVA (Plus Viewing Angle) mode accomplished the practical Wide Viewing Angle through the several technical phases. The multi-domain structure by the effect of fringe-field and the application of biaxial compensation film are the examples. PVA mode has a characteristic of high transmittance compared other Wide Viewing Angle mode. However the recent requirements of diversification of a use and the requirements of improvement of a screen quality make the transmittance diminished by modification the cell parameter and etc. In the experimentation hereunder the structure of Gradual Y-slit has accomplished over 10% of transmittance than the existing chevron pattern by applying this to T-pattern. And the produced 17″SXGA T-pattern panel shows the characteristics of 300 nits of brightness, 65% of color gamut, 600:1 contrast ratio and 25ms response time.

P‐24: Design of Low‐Cost 2.2‐inch qVGA LTPS TFT‐LCD Panel

In this paper, 2.2-inch qVGA LTPS(Low Temperature Poly-Si) TFT-LCD panel driven by external output buffers is proposed to reduce the display system cost. The LTPS panel with external output buffers improves the yield because only the digital functions are integrated on the LTPS panel. This also achieves a small number of interconnection lines between external IC and the LTPS panel. Finally, display system cost can be reduced by lowering the cost of flexible PCBs(Printed Circuit Boards). Moreover, the proposed panel adopts 1:6 de-multiplexing scheme for decreasing the height of the source driver circuitries. Compared with the conventional structure of 1:3 de-multiplexing scheme, the height of the source driver area is reduced as much as 40%.

Development of thermal neutron SER-resilient high-k/metal gate technology

We report the experimental procedure and data that establishes the correlation between natural boron (B10) concentration and thermal neutron soft error rate (SER) in an advanced 28nm high-k/metal gate (HK/MG) technology node. Thermal neutron induced singe event upsets (SEU) depend on the concentration of B10 in the contact process adopted for boosting SRAM performance. However, as technology rapidly evolves in terms of transistor feature size and overall design complexity, B10 concentration needs to decrease so as to reduce thermal neutron SER risk. Optimization of contact and eSiGe process can provide a technology profile that is robust against thermal and high energy neutron SER.

Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance

This paper explores the effectiveness of error detection schemes in increasingly multiple-cell upset-dominant technologies, specifically SRAM. A review of interleaving distance, parity codes, and well-taps is conducted to examine each attribute. Then, the paper proposes a novel error detection scheme with the harmonious use of the multiple-cell upset inhibition effects of well-taps, the detectability of parity codes, and an interleaving distance scheme to create an effective error detection scheme that is both flexible and has a high implementation prospect. A row depth model is created to assess the effectiveness of the proposed scheme. The model shows that advanced technologies with greater multiple-cell upset sizes and ratios will experience error detection failures with schemes such as single error correction-double error detection, whereas the proposed scheme remains effective. Experimental data supports the premise that well-taps inhibit multiple-cell upset, as it is found that 1% cross well-taps. The proposed scheme is recognized to be at least three times better against error detection failures than single error correction-double error detection.

53.3: Multisync Poly‐Si AMLCD

We propose a new scan driver circuit to implement multi display mode(mutisync function), which uses an identical conventional scan driver circuit without an additional circuit. The new scheme is simple and takes a small area, compared with the prior schemes for multisync mode. We have fabricated 7-inch QVGA low-temperature Poly-Si TFT LCD employing our scan driver architecture and obtained good display images for normal mode and cinema mode.