Il Kwon Oh

Synthesis of wafer-scale uniform molybdenum disulfide films with control over the layer number using a gas phase sulfur precursor

We describe a method for synthesizing large-area and uniform molybdenum disulfide films, with control over the layer number, on insulating substrates using a gas phase sulfuric precursor (H2S) and a molybdenum metal source. The metal layer thickness was varied to effectively control the number of layers (2 to 12) present in the synthesized film. The films were grown on wafer-scale Si/SiO2 or quartz substrates and displayed excellent uniformity and a high crystallinity over the entire area. Thin film transistors were prepared using these materials, and the performances of the devices were tested. The devices displayed an on/off current ratio of 10(5), a mobility of 0.12 cm(2) V(-1) s(-1) (mean mobility value of 0.07 cm(2) V(-1) s(-1)), and reliable operation.

Static and Dynamic Performance of Complementary Inverters Based on Nanosheet α-MoTe2 p-Channel and MoS2 n-Channel Transistors

Molybdenum ditelluride (α-MoTe2) is an emerging transition-metal dichalcogenide (TMD) semiconductor that has been attracting attention due to its favorable optical and electronic properties. Field-effect transistors (FETs) based on few-layer α-MoTe2 nanosheets have previously shown ambipolar behavior with strong p-type and weak n-type conduction. We have employed a direct imprinting technique following mechanical nanosheet exfoliation to fabricate high-performance complementary inverters using α-MoTe2 as the semiconductor for the p-channel FETs and MoS2 as the semiconductor for the n-channel FETs. To avoid ambipolar behavior and produce α-MoTe2 FETs with clean p-channel characteristics, we have employed the high-workfunction metal platinum for the source and drain contacts. As a result, our α-MoTe2 nanosheet p-channel FETs show hole mobilities up to 20 cm(2)/(V s), on/off ratios up to 10(5), and a subthreshold slope of 255 mV/decade. For our complementary inverters composed of few-layer α-MoTe2 p-channel FETs and MoS2 n-channel FETs we have obtained voltage gains as high as 33, noise margins as high as 0.38 VDD, a switching delay of 25 μs, and a static power consumption of a few nanowatts.

Review of plasma-enhanced atomic layer deposition: Technical enabler of nanoscale device fabrication

With devices being scaled down to the nanometer regime, the need for atomic thickness control with high conformality is increasing. Atomic layer deposition (ALD) is a key technology enabler of nanoscale memory and logic devices owing to its excellent conformality and thickness controllability. Plasma-enhanced ALD (PE-ALD) allows deposition at significantly lower temperatures with better film properties than in conventional thermal ALD. These benefits make PE-ALD more attractive for nanoscale device fabrication. In this paper, the basic characteristics and film properties of PE-ALD processes will be reviewed, focusing on the application of PE-ALD in key components of nanoscale device fabrication: gate oxides, Cu interconnects, and nanoscale contacts.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics.

Effect of Al2O3 Deposition on Performance of Top-Gated Monolayer MoS2-Based Field Effect Transistor

Deposition of high-k dielectrics on two-dimensional MoS2 is an important process for successful application of the transition-metal dichalcogenides in electronic devices. Here, we show the effect of H2O reactant exposure on monolayer (1L) MoS2 during atomic layer deposition (ALD) of Al2O3. The results showed that the ALD-Al2O3 caused degradation of the performance of 1L MoS2 field effect transistors (FETs) owing to the formation of Mo-O bonding and trapping of H2O molecules at the Al2O3/MoS2 interface. Furthermore, we demonstrated that reduced duration of exposure to H2O reactant and postdeposition annealing were essential to the enhancement of the performance of top-gated 1L MoS2 FETs. The mobility and on/off current ratios were increased by factors of approximately 40 and 103, respectively, with reduced duration of exposure to H2O reactant and with postdeposition annealing.

In situ surface cleaning on a Ge substrate using TMA and MgCp2 for HfO2-based gate oxides

Comparative studies of the in situ surface cleaning effect on Ge substrates using trimethyl aluminum (TMA) and dicyclopentadienyl magnesium (MgCp2) were performed. The surface cleaning process is the direct exposure of either a TMA or MgCp2 precursor on a Ge surface prior to the deposition of a HfO2 gate dielectric. Also, we studied a HfO2/Al2O3 and MgO bilayer on uncleaned Ge using the same precursors for comparison with surface treatment. From the correlation of chemical composition, line profile, atomic scale imaging and electrical evaluation, MgCp2 was the most effective method for reducing Ge diffusion into the HfO2 dielectric layer via the efficient surface cleaning process. MgCp2 cleaning produces thermally-stable Ge oxides while TMA cleaning reduces all types of Ge sub-oxides. As a result, the process can form a thermally-stable interface layer primarily composed of Ge3+, leading to better electrical properties than TMA.

Fabrication of Transferable Al2O3 Nanosheet by Atomic Layer Deposition for Graphene FET

Without introducing defects in the monolayer of carbon lattice, the deposition of high-κ dielectric material is a significant challenge because of the difficulty of high-quality oxide nucleation on graphene. Previous investigations of the deposition of high-κ dielectrics on graphene have often reported significant degradation of the electrical properties of graphene. In this study, we report a new way to integrate high-κ dielectrics with graphene by transferring a high-κ dielectric nanosheet onto graphene. Al2O3 film was deposited on a sacrificial layer using an atomic layer deposition process and the Al2O3 nanosheet was fabricated by removing the sacrificial layer. Top-gated graphene field-effect transistors were fabricated and characterized using the Al2O3 nanosheet as a gate dielectric. The top-gated graphene was demonstrated to have a field-effect mobility up to 2200 cm(2)/(V s). This method provides a new method for high-performance graphene devices with broad potential impacts reaching from high-frequency high-speed circuits to flexible electronics.

Growth characteristics and electrical properties of SiO2 thin films prepared using plasma-enhanced atomic layer deposition and chemical vapor deposition with an aminosilane precursor

The deposition of high-quality SiO2 films has been achieved through the use of both plasma-enhanced chemical vapor deposition (PE-CVD) and plasma-enhanced atomic layer deposition (PE-ALD) methods using H2Si[N(C2H5)2]2 as a Si precursor. We systematically investigated growth characteristics, chemical compositions, and electrical properties of PE-CVD SiO2 prepared under various deposition conditions. The SiO2 films prepared using PE-CVD showed high purity and good stoichiometry with a dielectric constant of ~4. In addition, the PE-ALD process of the SiO2 films exhibited well-saturated and almost linear growth characteristics of ~1.3 Åxa0cycle−1 without notable incubation cycles, producing pure SiO2 films. Electrical characterization of metal-oxide silicon capacitor structures prepared with each SiO2 film showed that PE-ALD SiO2 films had relatively lower leakage currents than PE-CVD SiO2 films. This might be a result of the saturated surface reaction mechanism of PE-ALD, which allows a smooth surface in comparison with PE-CVD method. In addition, the dielectric properties of both SiO2 films were further evaluated in the structures of In–Ga–Zn–O thin-film transistors, and they both showed good device performances in terms of high Ionxa0−xa0Ioff ratios (>108) and low off-currents (<10−11xa0A). However, based on the negative bias stress reliability test, it was found that PE-ALD SiO2 showed better reliability against a negative Vth shift than PE-CVD SiO2, which might also be understood from its smoother channel/insulator interface generation at the interface.

The impact of atomic layer deposited SiO2 passivation for high-k Ta1−xZrxO on the InP substrate

Metal–oxide-semiconductor (MOS) capacitors with an amorphous Ta1−xZrxO composite gate dielectric film and a SiO2 passivation layer were fabricated on an indium phosphide (InP) substrate. To investigate the impact of the passivation layer, the interfacial chemical, physical and electrical properties of the Ta1−xZrxO/InP and Ta1−xZrxO/SiO2/InP MOS structures were studied in detail. Electrical conductivity measurements combined with chemical bonding analysis using X-ray photoelectron spectroscopy (XPS) and electron dispersive spectroscopy (EDS) were conducted in order to evaluate the suitability of a Ta1−xZrxO alloy as a gate dielectric film for an InP substrate. XPS results showed that the Ta1−xZrxO film retained its insulating characteristics and was thermally stable even after annealing at 500 °C. However, Fermi-level pinning and significant diffusion of indium through the Ta1−xZrxO were observed. The diffusion of In was remarkably reduced after introducing the SiO2 passivation layer, which resulted in an overall reduction in interfacial layer thickness. Parallel conductance contour measurements showed that the SiO2 passivation layer resulted in unpinning of the Fermi-level. The introduction of a SiO2 passivation layer with the Ta1−xZrxO composite gate dielectric film was found to provide remarkably improved dielectric performance, which was mainly attributed to reduced In diffusion and the passivation of interfacial and bulk dielectric defects.

Atomic layer deposition of HfO2 on graphene through controlled ion beam treatment

The polymer residue generated during the graphene transfer process to the substrate tends to cause problems (e.g., a decrease in electron mobility, unwanted doping, and non-uniform deposition of the dielectric material). In this study, by using a controllable low-energy Ar+ ion beam, we cleaned the polymer residue without damaging the graphene network. HfO2 grown by atomic layer deposition on graphene cleaned using an Ar+ ion beam showed a dense uniform structure, whereas that grown on the transferred graphene (before Ar+ ion cleaning) showed a non-uniform structure. A graphene–HfO2–metal capacitor fabricated by growing 20-nm thick HfO2 on graphene exhibited a very low leakage current (<10−11 A/cm2) for Ar+ ion-cleaned graphene, whereas a similar capacitor grown using the transferred graphene showed high leakage current.