Il-Suk Kang

Recovery improvement of graphene-based gas sensors functionalized with nanoscale heterojunctions

We report a development of reduced graphene oxide (rGO)-based gas sensors with a practical recovery by facile functionalization with tin dioxide nanoclusters. Upon the introduction of UV illumination to this nanostructure, the reaction on surfaces of tin dioxide nanoclusters was activated and thereby the nanoscale heterojunction barriers between the rGO sheet and the nanoclusters were developed. This lowered the conductance to quickly recover, which was intensified as the cluster density has reached to the percolation threshold. However, after the formation of the cluster percolating network, the sensor response has totally changed into a deterioration of the sensitivity as well as the recovery.

The Reduction of the Dependence of Leakage Current on Gate Bias in Metal-Induced Laterally Crystallized p-Channel Polycrystalline-Silicon Thin-Film Transistors by Electrical Stressing

The high dependence of the leakage current on the gate bias that is normally observed in metal-induced laterally crystallized polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) can be reduced effectively by electrical stressing. This brief examined the mechanism for the decrease in the high dependence of the leakage current on the gate bias in p-channel poly-Si TFTs by electrical stressing. This effect increased with increasing stress bias that is applied to the gate or drain. The effective decrease in leakage current dependence on the gate bias was attributed to electron trapping in the gate oxide during electrical stressing. It was found that this trapping occurred near the drain junction, and electron detrapping (or trap site regeneration) was also observed after annealing at temperatures above 350degC, resulting in an increase in leakage current. This brief proposes a device structure with a low dependence of the leakage current on the gate bias through light doping at the drain region.

Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain

We propose an offset-gated bottom gate polycrystalline silicon thin-film transistor (TFT), with a combination structure of ultrathin channel and raised source/drain, employing a simple process of the back surface exposure. It is experimentally and simulatively demonstrated that the new device has lower leakage current and better saturation characteristics, as compared with the conventional non offset TFT, due to the lateral electric field near the drain, which is reduced by the proposed structure. Moreover, the proposed TFT exhibits much better ON/OFF current ratio because the high current drive due to the raised source/drain structure is enough to compensate for the ON-state current reduction due to the offset-gate structure.

Bottom-gated metal-induced laterally crystallized silicon thin-film transistor with self-aligned raised source/drain

A bottom-gated metal-induced laterally crystallized silicon thin-film transistor with self-aligned raised source/drain has been fabricated and characterized. In order to achieve complete alignment of the thick source/drain to the gate, a simple process of back surface exposure was employed twice. It features a thin active channel region with fewer grains, resulting in a low grain boundary trap density and a thick source/drain region with a low lateral electric field as well as a low resistance. The proposed device simultaneously improves on the turn-on and -off currents, showing good saturation characteristics and good short-channel characteristics.

A Fabrication Method of Polycrystalline-Silicon Thin-Film Transistors with Contrastive Characteristics on One Substrate

We propose a method of fabricating an offset-gated bottom gate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) and a conventional one on one substrate. A successive etching process using the isotropy of wet etching is employed to self-align these structures without a high photolithographic step. According to the offset length the trade-off between the ON-state current and the leakage current is investigated. Experimental and simulated results indicate that the electrical properties of the proposed offset-gated TFT including a low leakage current compared with that of the conventional one by over two orders of magnitude are suitable for active matrix addressing elements.

A Method for Fabricating Practically Channel-Corner-Free Polycrystalline Silicon Thin-Film Transistors

The influences of metal-induced laterally crystallized silicon channel corners on the performance and reliability of thin-film transistors (TFTs) were investigated. It was found that the TFT with the channel width, mostly applied to active matrix organic light-emitting diodes, had weak immunity to electrical stresses because of the heaviest weight of silicide-rich channel corner on the channel width by the geometric effect. The proposed TFT fabrication, which is composed of two consecutive adjacent step switches, makes TFTs practically channel-corner-free, resulting in high reliability. Moreover, it enables TFTs to have more current flow paths that maintain a high performance.

Dynamic Characteristics of Multi-Channel Metal-Induced Unilaterally Precrystallized Polycrystalline Silicon Thin-Film Transistor Devices and Circuits

Electrical properties of multi-channel metal-induced unilaterally precrystallized polycrystalline silicon thin-film transistor (MIUP poly-Si TFT) devices and circuits were investigated. Although their structure was integrated into small area, reducing annealing process time for fuller crystallization than that of conventional crystal filtered MIUP poly-Si TFTs, the multi-channel MIUP poly-Si TFTs showed the effect of crystal filtering. The multi-channel MIUP poly-Si TFTs showed a higher carrier mobility of more than 1.5 times that of the conventional MIUP poly-Si TFTs. Moreover, PMOS inverters consisting of the multi-channel MIUP poly-Si TFTs showed high dynamic performance compared with inverters consisting of the conventional MIUP poly-Si TFTs.

Influence of lateral crystallization on gate oxide in polycrystalline silicon thin-film transistors

The phase transformation in a film influences its surrounding. In order to remove influences on gate oxide caused by metal-induced unilateral crystallization, a gate was formed after a lateral crystallization. The thin-film transistor (TFT) by the novel fabrication method was shown to have a higher current drive and better immunity to early drain breakdown, compared to the conventional TFT performed by a lateral crystallization and a dopant activation process at a time. These improvements are attributed to being free from the interface state generation at the interface between the gate oxide and the active silicon.

Low Thermal Budget Crystallization of Amorphous Silicon by Nanoclusters

A low thermal budget crystallization of amorphous-silicon (a-Si) film by nickel nanoclusters was investigated. At 400°C, which the already fabricated metal interconnects can endure, 5 nm sized clusters with densities of more than 2 × 10 10 cm -2 fully crystallized the a-Si film. From electron microscopies, although a single nanocluster produced a single-grain growth of up to 100 nm, its small Ni quantity could not induce lateral crystallization. From Raman spectroscopy, the crystalline volume fraction of a crystallized film was about 0.7, and this film showed passable Hall mobility of 4.55 cm 2 /V s.

Low Leakage Current Structures with Subgate in Metal-Induced Unilaterally Crystallized Silicon Thin-Film Transistors

Low leakage current structures, such as the lightly doped drain and the field-induced drain, employing a subgate were investigated. In order to achieve the self-alignment of a submicrometer level lightly doped drain, the transmittance change in the phase transformation of silicon by a metal-induced lateral crystallization method was employed. Due to an extended thermionic emission domain, more than one order of magnitude improvements in the leakage current at the practical off-state were obtained. Controlling the subgate dielectric resulted in a better on/off current ratio. Simulated results demonstrated that the proposed field-induced drain structure effectively suppressed the electric fields near the drain.