Shin-Hee Han

The Reduction of the Dependence of Leakage Current on Gate Bias in Metal-Induced Laterally Crystallized p-Channel Polycrystalline-Silicon Thin-Film Transistors by Electrical Stressing

The high dependence of the leakage current on the gate bias that is normally observed in metal-induced laterally crystallized polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) can be reduced effectively by electrical stressing. This brief examined the mechanism for the decrease in the high dependence of the leakage current on the gate bias in p-channel poly-Si TFTs by electrical stressing. This effect increased with increasing stress bias that is applied to the gate or drain. The effective decrease in leakage current dependence on the gate bias was attributed to electron trapping in the gate oxide during electrical stressing. It was found that this trapping occurred near the drain junction, and electron detrapping (or trap site regeneration) was also observed after annealing at temperatures above 350degC, resulting in an increase in leakage current. This brief proposes a device structure with a low dependence of the leakage current on the gate bias through light doping at the drain region.

A Fabrication Method for Reduction of Silicide Contamination in Polycrystalline-Silicon Thin-Film Transistors

A major cause of degradations in polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated by Ni metal-induced lateral crystallization (MILC) is known to be due to the presence of Ni silicides in the channel region. In this letter, we proposed a structure for the reduction of Ni silicides in the MILC region. Also, the electrical properties of poly-Si TFTs which were fabricated with the structure were investigated. It was found that the field-effect mobility and the leakage current of p-channel Ni seed MILC TFTs is significantly improved compared to TFTs fabricated by conventional MILC process.

Improvement of the electrical performance in metal-induced laterally crystallized polycrystalline silicon thin-film transistors by crystal filtering

The electrical performance of the polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is greatly affected by the microstructure of the poly-Si. The crystal filtering method is employed to improve the electrical properties of poly-Si TFTs using metal-induced lateral crystallization by the ordering of Si grains. Experimental results indicated that the field-effect mobility of TFTs having crystal filtered poly-Si is more than 2.5 times higher than that of conventional poly-Si TFTs. It is found that the ordered microstructure is one of the key parameters to improve the electrical performance in poly-Si TFTs.

Effects of Mechanical Stress on the Growth Behaviors of Metal-Induced Lateral Crystallization

Effects of external mechanical stress on the growth behaviors of metal-induced lateral crystallization (MILC) were investigated. Results showed that the MILC growth rate was four times faster by the tensile stress than without stress and two times slower by the compressive stress. In the microstructural analysis, needlelike grains were observed to grow along the direction when the tensile stress was applied, but wider grains grew in random directions when compressive stress was applied. These results confirm the applicability of the MILC growth model.

Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain

We propose an offset-gated bottom gate polycrystalline silicon thin-film transistor (TFT), with a combination structure of ultrathin channel and raised source/drain, employing a simple process of the back surface exposure. It is experimentally and simulatively demonstrated that the new device has lower leakage current and better saturation characteristics, as compared with the conventional non offset TFT, due to the lateral electric field near the drain, which is reduced by the proposed structure. Moreover, the proposed TFT exhibits much better ON/OFF current ratio because the high current drive due to the raised source/drain structure is enough to compensate for the ON-state current reduction due to the offset-gate structure.

Bottom-gated metal-induced laterally crystallized silicon thin-film transistor with self-aligned raised source/drain

A bottom-gated metal-induced laterally crystallized silicon thin-film transistor with self-aligned raised source/drain has been fabricated and characterized. In order to achieve complete alignment of the thick source/drain to the gate, a simple process of back surface exposure was employed twice. It features a thin active channel region with fewer grains, resulting in a low grain boundary trap density and a thick source/drain region with a low lateral electric field as well as a low resistance. The proposed device simultaneously improves on the turn-on and -off currents, showing good saturation characteristics and good short-channel characteristics.

The Electrical Properties of Unidirectional Metal-Induced Lateral Crystallized Polycrystalline-Silicon Thin-Film Transistors

It has been known that adjacent Pd enhances the crystallization rate in Ni metal-induced lateral crystallization (Ni-MILC) and this knowledge has been used to fabricate the unidirectional MILC thin-film transistors (TFTs), which eliminate the boundary formed at the center of TFT channel in a normal MILC TFTs. It is discovered that the MILC/MILC boundary (MMB) is responsible for the high leakage current and low field- effect mobility. The electrical properties of unidirectional MILC TFTs (Width/Length = 10/10 mum) improved considerably comparing to those of MILC TFTs containing the MMB. The leakage current and field-effect mobility, which have been regarded as obstacles for industrialization of the MILC process, measure to be 2.1 X 10-11 A and 83 cm2/ V ldr s, respectively.

A Fabrication Method of Polycrystalline-Silicon Thin-Film Transistors with Contrastive Characteristics on One Substrate

We propose a method of fabricating an offset-gated bottom gate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) and a conventional one on one substrate. A successive etching process using the isotropy of wet etching is employed to self-align these structures without a high photolithographic step. According to the offset length the trade-off between the ON-state current and the leakage current is investigated. Experimental and simulated results indicate that the electrical properties of the proposed offset-gated TFT including a low leakage current compared with that of the conventional one by over two orders of magnitude are suitable for active matrix addressing elements.