Ilya Levin

Scheduling a two-machine robotic cell: A solvable case

The paper deals with the scheduling of a robotic cell in which jobs are processed on two tandem machines. The job transportation between the machines is done by a transportation robot. The robotic cell has limitations on the intermediate space between the machines for storing the work-in-process. What complicates the scheduling problem is that the loading/unloading operation times are non-negligible. Given the total number of operationsn, an optimalO(n logn)-time algorithm is proposed together with the proof of optimality.

Self-checking Synchronous FSM Network Design with Low Overhead

A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead is developed. Checkers are used only for FSMs, which output lines are at the same time output lines of the network. The checkers observe output lines of these FSMs. The method is based on reducing the problem to a self-checking synchronous FSM design. The latter is provided by applying a special description of FSM namely, so-called unate Programmable Logic Array (PLAu) description. Single stuck-at fault on the FSM poles and gate poles are considered. PLA realization ofFSM allows a factorized or multilevel logic synthesis. They both provide a unidirectional manifestation of the above mentioned faults on the output lines of the corresponding FSMs. This realization also gives rise to a transparency of each component FSM of the network for the faults. PLA realization is derived from the State Transition Graph (STG) description of FSMs with using the m-out-of-n encoding of its states and insignificant expanding the products of STG. The problem of replacing an arbitrary synchronous FSM network for the self-checking one with low overhead is discussed.

Self-checking of FPGA-based control units

The paper introduces a new technique for on-line checking of FPGA based Control Units (CUs). This technique is based on the architecture comprising two portions. A self-checking CU and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination of an Evolution block and an Execution block. Comparison of code vectors being transferred between the blocks of the portions enables providing a totally self-checking property. The self-checking CU is implemented in a form of a one-rail network of interconnected pre-designed LUT-based configurable logical blocks. The self-checking checker is a Sum-Of-Minterms based checker. The proposed technique: a) does not require any encoding of output words; and b) uses one-rail design, thereby drastically decreasing the required overhead.

A multiple-constructs framework for teaching control concepts

The phenomenon of control is an essential component of the everyday natural, social, and artificial environment. Control-related concepts have become a central component of many core topics in modern technology education. Knowledge about students abilities to understand (analysis) and design (synthesis) controlled systems, however, is still poor. Evidence already collected shows that students have serious difficulties in transcending the phenomenal or behavioral understanding of a systems functioning toward more formal definitions of the control process. In this paper, a framework to start dealing with these and related issues is proposed. First, the nature of controlled systems is discussed. Then, a conceptual framework encompassing a variety of perspectives on and approaches to control is presented. The framework consists of two main components: the process component; and the representational component. The first relates to the stages in the process of defining and implementing control. The second is the repertoire of constructs used for defining and implementing control. Two main paradigms are suggested as the conveyors of very different cognitive approaches to control: programming; and design paradigms. Finally, the educational implications of the proposed framework at both the cognitive and the instructional levels are discussed.

Designing fault tolerant FSM by nano-PLA

The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area and the number of crosspoint devices, are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault tolerant nano-PLA based FSMs. The method is based on decomposing an initial PLA description of the FSM into a three interacting portions. The proposed solution provides significant reduction of the area without meaningful increasing of a number of crosspoint devices in comparison with known solutions and provides a trade-off between the area and the number of devices in designing FSMs by PLAs.

Survivable self-checking sequential circuits

This paper presents a method for designing totally self-checking synchronous sequential circuits (SSC), and investigates their behavior in presence of transient faults. We deal with the case when the circuit is able to recover after the number of clocks. We call SSC owing this property as a survivable SSC. A concept of a partially monotonous SSC is developed in the paper. It is proven that the partially monotonous SSCs are survivable.

Matrix Model of Logical Simulator Within Spreadsheet

Matrix model of logical simulator within spreadsheet This paper examines the use of spreadsheets for simulation of logical control units. A matrix model is proposed for this aim. The use of this model is appropriate both for teaching and learning of simulation of a specific type of integrated circuit — Programmable Logic Arrays — and also for any type of control unit representable in the form of a logical function system.

Use of gray decoding for implementation of symmetric functions

This paper discusses reduction of the number of product terms in representation of totally symmetric Boolean functions by Sum of Products (SOP) and Fixed Polarity Reed- Muller (FPRM) expansions. The suggested method reduces the number of product terms, correspondingly, the implementation cost of symmetric functions based on these expressions by exploiting Gray decoding of input variables. Although this decoding is a particular example of all possible linear transformation of Boolean variables, it is efficient in the case of symmetric functions since it provides a significant simplification of SOPs and FPRMs. Mathematical analysis as well as experimental results demonstrate the efficiency of the proposed method.

Behavioral Simulation of an Arithmetic Unit Using The Spreadsheet

Behavioral simulation and arithmetic unit using the spreadsheet This paper examines the use of spreadsheets for the construction of the behavioral simulation of Arithmetic Units. It is shown that the spreadsheet is appropriate both for teaching and learning of different types of Arithmetic Units. These units can be simulated very simply by students during the lesson.

Spreadsheets in teaching and learning topics in calculus

The use of spreadsheets in introducing students to the concept of a limit of a sequence is demonstrated and the possible computer‐based scenario as the enhancement of the teaching/learning process of calculus is exemplified. It is shown how the spreadsheets operational capability assists visualizing the Bolzano‐Cauchy principle of convergence and leads eventually to the possibility of employing computer technology in deciding the convergence of positive series.