Vladimir Ostrovsky

Cascade Scheme for Concurrent Errors Detection

The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided. An universal scheme of finite state machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement

Self-checking sequential circuits with self-healing ability

In this paper we deal with totally self-checking (TSC) synchronous sequential circuits (SSCs), that are able to recover after an occurrence of a fault. We call SSC owing this property as a self-healing SSC. A concept of a partially monotonic SSC is used in the paper. It is shown that the partially monotonic SSCs satisfy the self-healing property. A novel reduced m-out-of-n code is developed. It is proposed applying this code to the synthesis of a TSC checker for the state monotonic SSCs. The proposed method of synthesis is based on a LUT implementation of monotonic functions.For most circuits in a standard benchmark set, the proposed approach leads to a reduction of about 10-20% of the overhead as compared with the traditional methods.

Designing FPGA based self-testing checkers for m-out-of-n codes

The paper describes a specific method for designing self-checking checkers for m-out-of-n codes. The method is oriented to the field programmable gate arrays technology and is based on decomposing the sum-of-minterms corresponding to an m-out-of-n code. The self-testing property of the proposed checker is proven for a set of multiple stuck-at faults at input and output poles of a logic cell. An estimated complexity of obtained m-out-of-n checker demonstrates high efficiency of the proposed method.

Arbitrary Error Detection in Combinational Circuits by Using Partitioning

The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuits. It does not require any redundant coding variables; instead, it utilizes a sub-set of input variables. These variables are transferred directly into a checker providing the arbitrary error detection. The paper develops and studies a method for selecting an optimized sub-set of such variables. Benchmark results show efficiency of the proposed approach.

Programmable Comparators Based Array for Regular QCA Implementation

The paper presents a novel universal quantum cellular automata (QCA) gate called boundary comparator. This gate implements a Boolean function in its boundary form, which is a superposition of elementary boundary functions i.e. a threshold function having weights equal to integer powers of 2. The boundary comparators are arranged in a form of array forming homogeneous programmable structure. The paper proposes a method of synthesis of Boolean functions on the base of boundary functions. The method uses autocorrelation values of the initial function for minimization of a number of bounds. The structures of the boundary comparator as well as the structure of the comparator-based array are presented. Benchmark results allow evaluating efficiency of the proposed structure in comparison with known QCA solutions.

Self-healing ability of sequential circuits

We investigate architectures that enable circuits to survive without introducing any additional overhead. We deal with microcontrollers described by Finite State Machines (FSMs) and implemented as Synchronous Sequential Circuits (SSCs). We use the on-set realization of output and next state functions. Furthermore, we deal with implementations where both the next state and output equations are unate in state variables and binate in primary input variables. The proposed synthesis technique implements self-healing SSC and minimizes the required overhead. We investigate the techniques from the point of overheads, assuming that the resulting on-line checking controller will be implemented by a FPGA.

Designing Self-checking Circuits with Smooth Power Dissipation

The paper discuses a new approach for designing self-checking sequential circuits with smooth power dissipation The proposed approach enables achievement of circuits with a lower overhead. At the same time it provides for circuits a specific property to have approximately the same power dissipation on all codewords. A new architecture of the self-checking sequential circuit with smooth power dissipation is proposed. The architecture is investigated on a number of standard benchmarks.

Techniques for formal transformations of binary decision diagrams

Binary decision diagrams (BDDs), when used for the representation of discrete functions, permit the direct technology mapping into multi-level logic networks. Complexity of a network derived from a BDD is expressed by its number of non-terminal nodes. The paper discusses the problem of reducing the BDDs. It makes two main contributions: (a) the bounds of the potential complexity of the BDD are determined and proven; (b) a formal technique is presented for simplification of Boolean operations on a set of BDDs.

Teaching Reconfigurable Systems by RAM-Based FSM Designing

Reconfigurable systems have the potential to boost hardware performance, efficiency and to stimulate development activity by enabling designers to work with flexible “modeling clay”, rather than with fixed units of hardware. One of the design issues not widely covered in current Advanced Logic Design courses is the issue of reconfigurable systems design. The proposed pedagogical approach enables the achievement of reconfigurable electronic systems representations through Finite State Machine (FSM), and may be helpful for teaching disciplines, in subjects such as reconfigurable computing and advanced digital systems. The approach intends to cover topics such as architectures and capabilities of field-programmable logic devices; system specification, modelling, and synthesis of digital systems; design methodology; computer-aided design tools; reconfiguration techniques. FSMs are probably the most widely used control components in digital systems. The accepted FSM design methodology taught today is problem oriented, especially its combinatorial part. This approach makes changes to the design complicated and undesirable. In contrast, in the new suggested approach, the emphasis is on the automata behavior and not on its implementation logic. The result of this approach is a more flexible and less complicated design abilities that uplift the course to a more intense and focused levels while enabling at the same time to perform a larger amount of experiments, and enhance the students’ self-efficacy. The proposed design method for FSM implementation with both combinational part and state memory part is built primarily from RAM blocks. The basic components of the circuit are utilizing the FPGA’s RAM blocks, by reprogramming these one can provide for different functionality. The design procedure is automated by software shell that converts the FSM representation in Kiss2 format to a VHDL description that corresponds to the proposed architecture. This paper suggests methods for the design of a reconfigurable FSM to be used in Advanced Logic Design course, and deals with the following aspects: a) system formalization by high (behavioral) level of abstraction; b) RAM based FSM architecture; c) reusable templates d) software system for FSM static reconfiguration. In addition, the proposed approach enables non-hardware background people to be able to control algorithm representation as FSMs and it also provides an additional motivation for students since the reconfigurable systems concept may be linked to studies in other disciplines; and a dynamic reconfiguration is overviewed.Copyright

Reduction of Fault Latency in Sequential Circuits by using Decomposition

The paper discusses a novel approach for reduction of fault detection latency in a self-checking sequential circuit. The Authors propose decomposing the finite state machine (FSM) which describes the sequential circuit of interest, thus obtaining a number of component FSMs respectively describing the number of component circuits. Being decomposed to the number of component circuits, the initial circuit becomes able to detect faults much faster since, at each specific moment of time, one of the component circuits (FSMs) is working and all the others are being tested. The paper deals with the following aspects: a) the decomposition procedure; b) evaluation of the proposed approach based on a fault injection simulation; c) estimation of trade-off between the reduction of latency and the required hardware overhead. Results of the study are tested on a number of standard benchmarks.