Imran Ahmed

An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage

A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 104 clock cycles.

A 50-MS/s (35 mW) to 1-kS/s (15 /spl mu/W) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation

A novel rapid power-on operational amplifier and a current modulation technique are used in a 10-bit 1.5-bit/stage pipelined ADC in 0.18-/spl mu/m CMOS to realize power scalability between 1 kS/s (15 /spl mu/W) and 50 MS/s (35 mW), while maintaining an SNDR of 54-56 dB for all sampling rates. The current modulated power scaling (CMPS) technique is shown to enhance the power scaleable range of current scaling by 50 times, allowing ADC power to be varied by a factor of 2500 while only varying bias currents by a factor of 50. Furthermore, the nominal power is reduced by 20%-30% by completely powering off the rapid power-on opamps during the sampling phase in the pipelines sample-and-holds.

A Low-Power Capacitive Charge Pump Based Pipelined ADC

A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves >10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 ¿m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.

A High Bandwidth Power Scalable Sub-Sampling 10-Bit Pipelined ADC With Embedded Sample and Hold

A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented. The ADC uses a technique to eliminate the front-end sample hold, thereby reducing power consumption. The technique allows for a power savings of 20% compared to a previous design. A method to improve the settling behavior of rapid power-on opamps is also presented. Measured results in a 1.8 V 0.18 CMOS process verify the removal of the front-end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With 50 MS/s, for the SNDR is 51.5 dB, and with 4.55 MS/s for the SNDR is 52.2 dB.

An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage

A technique to rapidly correct for DAC errors in the multi-bit first stage of an 11-bit pipelined ADC is presented. Using a split-ADC approach the digital background scheme is validated with a proof-of-concept prototype fabricated in 1.8 V 0.18 mum CMOS, where the calibration scheme improves the INL of the ADC at fs=45 MS/s, from +6.1/-6.4 LSB to +1.1/-1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in ~104 clock cycles.

A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps

In the interest of extending battery life in mobile systems that use pipelined ADCs, several power-efficient pipelined ADCs have recently been proposed. The most promising topologies reported thus far are those that substitute the opamp, which is the largest consumer of power in pipelined ADCs, with alternative and more power-efficient circuits. However, opamp-less pipelined ADCs thus far either: 1) require complex nonlinear calibration [1], 2) are single-ended [2], 3) are pseudo-differential [3], or 4) require a sampling scheme that limits linearity (less than 8b ENOB in [3]). In this paper, a low-power pipelined ADC is presented that has significantly lower power consumption than many previous 10b ADCs in the mid-to-high speed range. The ADC does not require power-hungry opamps, and hence achieves similar power savings as in [1–3]. However, unlike prior opamp-free topologies, the ADC: 1) requires only stage-gain digital calibration, 2) uses fully differential pipelined stages, and 3) uses a sampling scheme that can achieve high linearity (SFDR of 66dB and better than 9b ENOB).

A 50 MS/s (35 mW) to 1 kS/s (15 /spl mu/W) power scaleable 10b pipelined ADC with minimal bias current variation

A new opamp with a short power-on time is used in a 10b 1.5b/stage power scalable pipelined ADC in 0.18 /spl mu/m CMOS. A current modulation technique is used so that as the power is varied from 15 /spl mu/W (at 1 kS/s) to 35 mW (at 50 MS/s) the bias currents only increase by a factor of 50. The SNDR is 54 to 56 dB for all sampling rates.

A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold

A pipelined ADC architecture for use in sub-sampled systems which has its power scaleable with down sampled bandwidth is presented. Using a technique developed to eliminate the front end sample and hold, a power savings of >20% is achieved compared to a previous design. A technique to improve the settling behavior of Rapid Power on Opamps is also presented. Measured results in 1.8V 0.18 mum CMOS verify the removal of the front end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With fs=50 MS/s, for fin=79 MHz the SNDR is 51.5 dB, and with fs=4.55 MS/s for fin=267 MHz the SNDR is 52.2 dB.

A 3-axis PZT-based MEMS gyroscope in 0.18μm CMOS

A 3-axis interface for a PZT-based MEMS gyroscope uses a PLL-less architecture and does not require high-voltage devices nor charge-pumps. The use of PZT in the MEMS enables a low-cost package which does not require the MEMS to be vacuum sealed. A single amplifier is used to simultaneously amplify actuation and Coriolis signals, thereby maintaining orthogonal phase between the signals. The ASIC has an inherent Allan variance of 0.13 °/s/√Hz, and 1, 0.35, and 0.66 °/s/√Hz for the ASIC plus x, y, and z axes respectively. The ASIC utilizes 6.2mA of current and 6.22mm2 of total area (including I/Os).

DAC nonlinearity and residue gain error correction in a pipelined ADC using a split-ADC architecture

A split-ADC architecture is used to calibrate both the non-linearity errors introduced by capacitor mismatches in the DAC, and gain errors in the residue amplifier of the first stage in a pipelined ADC. The background scheme only requires 105 clock cycles to perform the calibration to more than 12b accuracy. Simulated in Simulink and Spice, the digital calibration scheme improves the ADCs SNDR/SFDR from 54dB/58dB before calibration to 78dB/85dB after calibration