David A. Johns

Time-interleaved oversampling A/D converters: theory and practice

In this paper, the design procedure and practical issues regarding the realization of time-interleaved oversampling converters are presented. Using the concept of block digital filtering, it is shown that arbitrary /spl Delta//spl Sigma/ topologies can be converted into corresponding time-interleaved structures. Practical issues such as finite opamp gain, mismatching, and DC offsets are addressed, analyzed, and practical solutions to overcome some of these problems are discussed. To verify the theoretical results, a discrete-component prototype of a second-order time-interleaved /spl Delta//spl Sigma/ analog/digital (A/D) converter has been implemented and the design details as well as experimental results are presented.

Continuous-time LMS adaptive recursive filters

An approach for implementing continuous-time adaptive recursive filters is presented. The resulting filters should be capable of operating on much higher signal frequencies than their digital counterparts since no sampling is required. With respect to implementation problems, the effects of DC offsets are investigated and formulas derived so that these effects can be estimated and reduced. It is shown that the DC offset performance is strongly affected by the choice of structure for the adaptive filter. Experimental results from a discrete prototype are given where accurate adaption is observed and DC offset effects are compared to theoretical predictions. >

A high-quality analog oscillator using oversampling D/A conversion techniques

This paper describes a high-quality analog oscillator for low-frequency applications, which uses a combination of over-sampling and delta-sigma modulation. With the exception of a lowpass filter and a 1-bit D/A, the proposed circuit is entirely digital, providing accurate control over the oscillation frequency and amplitude. At the core of the oscillator is a digital simulation of an LC-tank circuit consisting of two cascaded integrators. This arrangement guarantees oscillation by constraining the poles of the resonator to locations on the z-plane unit-circle, even in a finite-precision implementation. To minimize circuit complexity, the entire oscillator is operated at the oversampled rate, thereby eliminating the associated interpolation filter. Furthermore, the incorporation of a delta-sigma modulator inside the resonator loop leads to a very efficient implementation requiring only 4 multi-bit adders and a 2-input multiplexor. The desired analog signal may be recovered by lowpass filtering the 1-bit output of the delta-sigma modulator. Experiments performed thus far have indicated an effective dynamic range exceeding 80 dB. >

Design and analysis of delta-sigma based IIR filters

Design techniques for IIR filters operating on oversampled delta-sigma ( Delta Sigma ) modulated signals are presented. It is shown that Delta Sigma -based IIR filters can be efficiently realized by eliminating all multibit multipliers through the use of remodulating internal filter states. Noise results are presented showing that linear noise analysis gives excellent predictions of the noise performance over the frequency band of interest. It is also shown that latency and computational complexity can be reduced in some VLSI applications where digital representations of analog signals exist using oversampled Delta Sigma converters. >

On the implementation of input-feedforward delta-sigma modulators

This brief addresses some practical issues on the implementation of the input-feedforward delta-sigma modulators. First, the timing constraint imposed by the input-feedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog adder needed before the quantizer are explained and a method to eliminate the adder is proposed

An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage

A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 104 clock cycles.

A 50-MS/s (35 mW) to 1-kS/s (15 /spl mu/W) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation

A novel rapid power-on operational amplifier and a current modulation technique are used in a 10-bit 1.5-bit/stage pipelined ADC in 0.18-/spl mu/m CMOS to realize power scalability between 1 kS/s (15 /spl mu/W) and 50 MS/s (35 mW), while maintaining an SNDR of 54-56 dB for all sampling rates. The current modulated power scaling (CMPS) technique is shown to enhance the power scaleable range of current scaling by 50 times, allowing ADC power to be varied by a factor of 2500 while only varying bias currents by a factor of 50. Furthermore, the nominal power is reduced by 20%-30% by completely powering off the rapid power-on opamps during the sampling phase in the pipelines sample-and-holds.

A Low-Power Capacitive Charge Pump Based Pipelined ADC

A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves >10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 ¿m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.

A CMOS 10-gb/s power-efficient 4-PAM transmitter

A novel power-efficient architecture for a multilevel pulse amplitude modulation (PAM) transmitter is proposed. A data-look-ahead technique is used to pre-switch the current sources so that drive current is reduced when transmitting small voltage levels. This technique also eliminates the need for a pre-driver block, which also saves transmitter power. Based on this architecture, a 4-PAM transmitter is designed in 0.18-/spl mu/m standard digital CMOS technology. The transmitter achieves 3.5 GS/s (7 Gb/s) with a 1.7-V supply and 5 GS/s (10 Gb/s) with a 2-V supply and it occupies an area of 0.16 mm/sup 2/. The output driver and the entire transmitter consume only 11.25 and 66 mW at 7 Gb/s (20 and 121 mW at 10 Gb/s), respectively, which are the lowest reported powers at this speed.

A multilevel modulation scheme for high-speed wireless infrared communications

To investigate short-distance, point-to-point, infrared channels, a test-bench and circuits were constructed to determine the limitations of existing optoelectronics. The results of these measurements are used to formulate a channel model which is employed for the subsequent analysis of candidate bandwidth efficient modulation schemes. A new multilevel modulation scheme, Adaptively Biased QAM (AB-QAM), is proposed which has an asymptotic 3 dB SNR improvement over PAM and a 4.5 dB improvement over QAM for large constellations while maintaining the same bandwidth efficiency. Expressions are derived for the performance of each modulation scheme and are verified in simulation.