Imran Ali Shah

A chip set for lossless image compression

The authors describe two chips which form the basis of a high-speed lossless image compression/decompression system. They present the transform and coding algorithms and the main architectural features of the chips and outline some performance specifications. Lossless compression can be achieved by a transformation process followed by entropy coding. The two application-specific integrated circuits (ASICs) perform S-transform image decomposition and the Lempel-Ziv (L-Z) type of entropy coding. The S-transform, besides decorrelating the image, provides a convenient method of hierarchical image decomposition. The data compressor/decompressor IC is a fast and efficient implementation of the L-Z algorithm. The chips can be used independently or together for image compression. >

Bit-rate control for MPEG encoders

Abstract Bit-rate control is a central problem in designing image sequence compression systems. In this paper we describe a new approach to bit-rate control for inter-frame encoders such as MPEG encoders. This approach uses concepts from control theory. Its central feature is a surprisingly simple but effective model for the encoder, which consists of a gain element, a delay element and additive noise. In our system we control the bit-rate with a PI-controller which is set to achieve two objectives: (1) we want the picture quality to be as uniform as possible, and (2) we want to use as closely as possible the available amount of bits. It is demonstrated in the paper that these two objectives, when considered separately, lead to contradictory settings of the controller. This dilemma can be solved by using Bit Usage Profiles that indicate how the bits have to be spread over the pictures. The effectiveness of the approach is demonstrated by designing a bit-rate control for an MPEG encoder that has a nearly constant bit-rate per group of pictures (GOP). Such a bit-rate control is of high value for applications like magnetic recording, where a constant bit-rate per GOP is required in order to realize playback trick modes, e.g. the fast forward mode.

A group theoretic approach to multidimensional filter banks: theory and applications

In this paper, we provide a new method for analyzing multidimensional filter banks. This method enables us to solve various open problems in multidimensional filter bank characterization and design. The essential element in this new approach is the redefinition of polyphase components. It will be shown that a rich set of mathematical tools, in particular algebraic group theory, will become available for use in the analysis of filter banks. We demonstrate the elegance and power of the tool set by employing it for the characterization of multidimensional filter banks and applying it to two open problems. The first problem is concerned with the development of a general method to design multichannel (/spl ges/2), multidimensional filter banks using transformations, while the second problem is concerned with the derivation of general restrictions on group delays in linear phase filter banks. The treatment of these problems is only an illustration of the power of the tool set of algebraic group theory, employed for the first time in the context of multidimensional filter banks.

On ladder structures and linear phase conditions for bi-orthogonal filter banks

Some results for multidimensional m-band bi-orthogonal filter banks are presented. In the first part of the paper the authors introduce the ladder structure as a method for the design and implementation of the aforementioned filter banks. The second part of the paper focuses upon enforcing linear phase (LP) conditions in the context of ladder structures. The formulation of the LP conditions is done with the help of an algebraically oriented method for describing multidimensional filter banks. It is shown that in this notation, ladder structures allow a natural formulation of LP conditions.<<ETX>>

A Fast Multiplierless Architecture for General Purpose VLSI FIR Digital Filters

A multiplierless algorithm for calculating the convolution of a Finite Impulse Response (FIR) digital filter is presented. The algorithm is based on the partial slicing of input data vector words and performing the convolution in a distributed fashion. A fast, flexible and hardware efficient architecture for implementing the algorithm is described. Simulation results of the prototype one tap filter are presented, demonstrating the high speed capability of the architecture.

On constructing regular filter banks from domain bounded polynomials

The design of regular two-channel bi-orthogonal filter banks is shown to be reducible to the design of pairs of real polynomials with domain bounded to the interval /spl lsqb//spl minus/1,1/spl rsqb/. Techniques for designing polynomials satisfying various constraints are outlined. Transformation of polynomials to multidimensional bi-orthogonal filter banks is presented. >

A chip-set for lossless image compression

Two chips have been developed for lossless image compression. The first IC performs a transformation, and the second performs lossless coding. This work presents the transform and coding algorithms and the main architectural features of the chips, and outlines some performance specifications. The image compression/decompression system described reduces storage requirements in high-speed image archival and database applications and speeds the transmission of digital images over communication channels.<<ETX>>

A transform coding chip set for image compression

Two application-specific integrated circuits (ASICs) were designed to perform hierarchical transformation (S-transform processor) and Lempel-Ziv entropy coding (data compressor/decompressor). The chips can be used independently or together as a transform coding chip set for image compression. The algorithms and chip architectures of the transform codec (S-transform processor) and the entropy codec (data compressor/decompressor) are described.<<ETX>>

Data compressor decompressor IC

The data compressor decompressor (DCD) IC, a VLSI implementation of a version of the Lempel-Ziv (L-Z) compression algorithm, is discussed. The IC is suitable for high-speed, lossless compression of digital data such as text and images. The single-pass lossless compression scheme adapts to the statistics of the data being processed. The authors outline the L-Z compression method, illustrate a solution to its search requirement, and discuss the chip architecture and features.<<ETX>>

VLSI chip set for picture archiving and communication systems

Two Application Specific Integrated Circuits (ASIC) have been developed for hierarchical representation and compression of medical images for Picture Archiving & Communication System (PACS) environments. Hierarchical image representation enables progressive transmission of images and provides an economic means of rapidly surveying several images simultaneously. Furthermore, it facilitates the adaptation of high resolution images to displays with lower resolution. Compression enables efficient use of storage media and transmission channel capacities. Together the chip set implements a loss-less transform coding system.The first device implements the S-Transform algorithm (a 2x2 pixel case of the Hadamard Transform) which creates a hierarchical representation of an image. The second device implements the Lempel-Ziv compression algorithm, an adaptive codec that maps variable length strings of characters to fixed length code words. Used in tandem the chip set achieves image processing rates of up to 7.5million pixels per second at a system clock rate of 10MHz, for 13 bit pixel digitization. Both chips are microprocessor programmable. Because of the limited modes of the algorithm the S-Transform chip implementation focused on efficient utilization of silicon area and high processing rate. On the other hand because of its potential use outside of imaging applications, the Lempel-Ziv codec focused on versatility and speed. We describe the architecture and features of each chip and the characteristics of a system designed around these devices.