Brian C. Johnson

A chip set for lossless image compression

The authors describe two chips which form the basis of a high-speed lossless image compression/decompression system. They present the transform and coding algorithms and the main architectural features of the chips and outline some performance specifications. Lossless compression can be achieved by a transformation process followed by entropy coding. The two application-specific integrated circuits (ASICs) perform S-transform image decomposition and the Lempel-Ziv (L-Z) type of entropy coding. The S-transform, besides decorrelating the image, provides a convenient method of hierarchical image decomposition. The data compressor/decompressor IC is a fast and efficient implementation of the L-Z algorithm. The chips can be used independently or together for image compression. >

A chip-set for lossless image compression

Two chips have been developed for lossless image compression. The first IC performs a transformation, and the second performs lossless coding. This work presents the transform and coding algorithms and the main architectural features of the chips, and outlines some performance specifications. The image compression/decompression system described reduces storage requirements in high-speed image archival and database applications and speeds the transmission of digital images over communication channels.<<ETX>>

A transform coding chip set for image compression

Two application-specific integrated circuits (ASICs) were designed to perform hierarchical transformation (S-transform processor) and Lempel-Ziv entropy coding (data compressor/decompressor). The chips can be used independently or together as a transform coding chip set for image compression. The algorithms and chip architectures of the transform codec (S-transform processor) and the entropy codec (data compressor/decompressor) are described.<<ETX>>

Data compressor decompressor IC

The data compressor decompressor (DCD) IC, a VLSI implementation of a version of the Lempel-Ziv (L-Z) compression algorithm, is discussed. The IC is suitable for high-speed, lossless compression of digital data such as text and images. The single-pass lossless compression scheme adapts to the statistics of the data being processed. The authors outline the L-Z compression method, illustrate a solution to its search requirement, and discuss the chip architecture and features.<<ETX>>