In-Chul Hwang

Optical image encryption via photon-counting imaging and compressive sensing based ptychography

In this study, we investigate the integration of compressive sensing (CS) and photon-counting imaging (PCI) techniques with a ptychography-based optical image encryption system. Primarily, the plaintext real-valued image is optically encrypted and recorded via a classical ptychography technique. Further, the sparse-based representations of the original encrypted complex data can be produced by combining CS and PCI techniques with the primary encrypted image. Such a combination takes an advantage of reduced encrypted samples (i.e., linearly projected random compressive complex samples and photon-counted complex samples) that can be exploited to realize optical decryption, which inherently serves as a secret key (i.e., independent to encryption phase keys) and makes an intruder attack futile. In addition to this, recording fewer encrypted samples provides a substantial bandwidth reduction in online transmission. We demonstrate that the fewer sparse-based complex samples have adequate information to realize decryption. To the best of our knowledge, this is the first report on integrating CS and PCI with conventional ptychography-based optical image encryption.

A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load

This paper presents a digital low-dropout regulator (D-LDO) with a proposed transient-response boost technique, which enables the reduction of transient response time, as well as overshoot/undershoot, when the load current is abruptly drawn. The proposed D-LDO detects the deviation of the output voltage by overshoot/undershoot, and increases its loop gain, for the time that the deviation is beyond a limit. Once the output voltage is settled again, the loop gain is returned. With the D-LDO fabricated on an 110-nm CMOS technology, we measured its settling time and peak of undershoot, which were reduced by 60% and 72%, respectively, compared with and without the transient-response boost mode. Using the digital logic gates, the chip occupies a small area of 0.04 mm2, and it achieves a maximum current efficiency of 99.98%, by consuming the quiescent current of 15 μA at 0.7-V input voltage.

A Switchless Zigbee Frontend Transceiver With Matching Component Sharing of LNA and PA

This letter presents a low power and low cost RF transceiver for Zigbee standard (IEEE 802.15.4) using a switchless front-end configuration. It is enabled by designing the matching networks that a low noise amplifier and a power amplifier can share. The transceiver has been implemented in 1P6M 0.18 μm CMOS process. The receiver achieves 4.4 dB NF, -6.5 dBm IIP3 and 25.7 dB gain with 3-step digital gain controllability, while drawing 4.9 mA from 1.8 V power supply. The power amplifier dissipates 5 mA from 1.8 V power supply at 3 dBm output power and 16.5% EVM at worst, having 21 dB digital gain controllability. The die area is 1 mm × 1 mm.

A 0.93-mA Spur-Enhanced Frequency Synthesizer for L1/L5 Dual-Band GPS/Galileo RF Receiver

A versatile frequency synthesizer for a L1/L5 dual-band GPS/Galilleo dual-mode RF receiver is designed with a 0.13 ¿m CMOS process. For spur reduction, a simple low-glitch charge-pump circuit (CPC) is proposed in this letter. The fabricated chip achieves the in-band phase noise of -92 dBc/Hz and the spur performance of -71.23 dBc at 8.184 MHz offset from 1.571 GHz carrier with a second-order loop filter.

A 0.236 mm

A broad-band frequency synthesizer for L1/L5 dual-band GPS RF receiver is designed using a four-stage differential ring voltage controlled oscillator (VCO) with an on-chip regulator to compensate for variation by supply and temperature. Also, a pole-zero scalable loop filter is proposed to tune the loop bandwidth while keeping damping factor against wide variations of VCO gain. The proposed frequency synthesizer fabricated on a 90 nm CMOS process occupies 0.236 mm2 and consumes 3.99 mW at 1.2 V. The measured phase noise is less than -85 dBc/Hz for all bands.

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This paper describes an LED driver IC based on a digitally-controlled boost converter for LCD backlighting. We propose a new time-based analog-to-digital Converter (ADC) with variable quantization steps and a lowest voltage selector (LVS) based on the time-digitizing circuits to secure continuous conduction mode (CCM) operation of the boost converter. The proposed ADC and LVS can be fully implemented on a small silicon area and is suitable to low power controller for LED driver IC. The 2-channel LED driver IC fabricated on a 0.35um BCD process occupies the active area of 1.35mm2 including the entire compensation filter. The maximum efficiency is measured to be 90% or more and the start-up settling time is within 800μs.

, 3.99 mW Fully Integrated 90 nm CMOS L1/L5 GPS Frequency Synthesizer Using a Regulated Ring VCO

This paper presents an active current regulator for LED driver IC. The proposed driver circuit is consists of DC-DC converter for supplying constant DC voltage to LED, active current regulator for compensating channel-to-channel current error from LED strings and feedback circuit for controlling duty ratio of the converter. The proposed active current regulator senses current of LED channels by equalizing both and at LED current control transistor. Because the proposed circuit directly measures the LED channel current without a sensing resistor and regulates all channel with same regulation loop, the power consumption and the current error are much small compared with previous works. The measured maximum efficiency of overall LED driver IC is approximately 94% and current error of LED channel-to-channel is under . The proposed LED driver IC is fabricated Dongbu 0.35um BCD process.

A low-power and low-cost digitally-controlled boost LED driver IC for backlights

A broadband radio frequency synthesizer for multi-band, multi-standard mobile DTV tuners is proposed, it’s loop bandwidth can be calibrated to optimize integrated phase noise performance without the problem of phase noise peaking. For this purpose, we proposed a new third-order scalable loop filter and a scalable charge pump circuit to minimize the variation in phase margin during calibration. The prototype phase-lock loop is fabricated in 180nm complementary metal-oxide semiconductor shows that it effectively prevents phase noise peaking from growing while the loop bandwidth increases by up to three times.

Design of an Active Current Regulator for LED Driver IC

To remove the noise folding effect, which is a primary cause of degradation of the close-in phase noise of fractional-N phase-locked loops (PLLs) that use sigma-delta modulation, a fractional-N frequency synthesizer for broad-band and multi-standard mobile TV tuners was designed. The proposed skewed-reset phase frequency detector (SRPFD) provides a key solution to the problem of noise folding by enhancing the linearity of the phase frequency detection path through the charge pump (CP). Degradation of the reference spur—the unwanted effect in SR-PFDs— is blocked through the use of a sampled loop filter. An SR-PFD in a frequency synthesizer fabricated on a 180 nm CMOS process enhanced phase noise by 10 dB or more by using a multi stage noise shaper (MASH) 1-1-1 sigma-delta modulator (SDM), while a sampled loop filter decreased the amplitude of the reference spur by 7–13 dB.

A Stability-Secured Loop Bandwidth Controllable Frequency Synthesizer for Multi-Band Mobile DTV Tuners

A multi-band low phase noise CMOS voltage controlled oscillator (VCO) with wide frequency tuning range is presented for LTE standard. For very wide tunability, Hybrid Inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach improves phase noise and tuning range characteristics without additional area loss. The concept is demonstrated through the design of an LC VCO in a 65nm CMOS technology. Simulation results show that the proposed multi-band VCO operates from 2.5 GHz to 5.5 GHz with phase noise of -127 and -123 dBc/Hz at 1 MHz offset frequency, respectively and consumes 8.5 mA from 1.2 V supply.