Byung-Geun Lee

A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC

A low-power 14-b 100-MS/s analog-to-digital converter (ADC) is described. The prototype ADC achieves low-power consumption and small die area by sharing an opamp between two successive pipeline stages. Further reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique. The ADC, implemented in a 0.18-mum dual-gate-oxide (DGO) CMOS technology, achieves 72.4-dB signal-to-noise and distortion ratio, 88.5-dB spurious free dynamic range, and 11.7 effective number of bits at full sampling rate with a 46-MHz input while consuming 230-mW from a 3-V supply.

Neuromorphic Hardware System for Visual Pattern Recognition With Memristor Array and CMOS Neuron

This paper presents a neuromorphic system for visual pattern recognition realized in hardware. A new learning rule based on modified spike-timing-dependent plasticity is also presented and implemented with passive synaptic devices. The system includes an artificial photoreceptor, a Pr0.7Ca0.3MnO3-based memristor array, and CMOS neurons. The artificial photoreceptor consisting of a CMOS image sensor and a field-programmable gate array converts an image into spike signals, and the memristor array is used to adjust the synaptic weights between the input and output neurons according to the learning rule. A leaky integrate-and-fire model is used for the output neuron that is built together with the image sensor on a single chip. The system has 30 input neurons that are interconnected to 10 output neurons through 300 memristors. Each input neuron corresponding to a pixel in a 5 × 6 pixel image generates voltage pulses according to the pixel value. The voltage pulses are then weighted and integrated by the memristors and the output neurons, respectively, to be compared with a certain threshold voltage above which an output neuron fires. The system has been successfully demonstrated by training and recognizing number images from 0 to 9.

Electronic system with memristive synapses for pattern recognition

Memristive synapses, the most promising passive devices for synaptic interconnections in artificial neural networks, are the driving force behind recent research on hardware neural networks. Despite significant efforts to utilize memristive synapses, progress to date has only shown the possibility of building a neural network system that can classify simple image patterns. In this article, we report a high-density cross-point memristive synapse array with improved synaptic characteristics. The proposed PCMO-based memristive synapse exhibits the necessary gradual and symmetrical conductance changes, and has been successfully adapted to a neural network system. The system learns, and later recognizes, the human thought pattern corresponding to three vowels, i.e. /a /, /i /, and /u/, using electroencephalography signals generated while a subject imagines speaking vowels. Our successful demonstration of a neural network system for EEG pattern recognition is likely to intrigue many researchers and stimulate a new research direction.

A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-

A pipelined analog-to-digital converter (ADC) architecture which is suitable for low power and small area is presented. The prototype ADC achieves 10-bit resolution with only two opamps by removing a front-end sample-and-hold amplifier (SHA) and sharing an opamp between two successive pipeline stages. The errors from the absence of SHA and opamp-sharing are greatly reduced by the proposed techniques and circuits. Further reduction of power and area is achieved by using a capacitor-sharing technique and variable- variable-gm opamp. The ADC is implemented in 0.18 mum CMOS technology and occupies a die area of 0.86 mm2. The differential and integral nonlinearity of the ADC are less than 0.39 LSB and 0.81 LSB, respectively, at full sampling rate. The ADC achieves 56.2 dB signal-to-noise plus distortion ratio, 72.7 dB spurious free dynamic range, -66.2 dB total harmonic distortion, 9.03 effective number of bits for a Nyquist input at full sampling rate, and consumes 12 mW from a 1.8 V supply.

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Efforts to develop scalable learning algorithms for implementation of networks of spiking neurons in silicon have been hindered by the considerable footprints of learning circuits, which grow as the number of synapses increases. Recent developments in nanotechnologies provide an extremely compact device with low-power consumption.In particular, nanoscale resistive switching devices (resistive random-access memory (RRAM)) are regarded as a promising solution for implementation of biological synapses due to their nanoscale dimensions, capacity to store multiple bits and the low energy required to operate distinct states. In this paper, we report the fabrication, modeling and implementation of nanoscale RRAM with multi-level storage capability for an electronic synapse device. In addition, we first experimentally demonstrate the learning capabilities and predictable performance by a neuromorphic circuit composed of a nanoscale 1 kbit RRAM cross-point array of synapses and complementary metal-oxide-semiconductor neuron circuits. These developments open up possibilities for the development of ubiquitous ultra-dense, ultra-low-power cognitive computers.

Opamp

The prototype ADC is implemented in 0.18mum dual gate-oxide (DGO) CMOS technology and achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input while consuming 230mW from a 3V supply. Recently, power saving has been achieved by removing the explicit active S/H. Instead of removing the S/H, this work solves these drawbacks by merging the active S/H amplifier with the first MDAC (SMDAC). Thus, the ADC achieves low-power operation without sacrificing speed or accuracy.

Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device

We demonstrate a multispectral double-image-based cryptosystem that exploits only a tiny number of random white noise samples for proper decryption. Primarily, one of the two downsampled images is converted into the phase function after being shuffled by Arnold transform (AT), while the other image is modulated as an amplitude-based image after AT. Consecutively, a full double-image encryption can be achieved by employing classical double random phase encryption (DRPE) technique in the fractional Fourier transform domain with corresponding fractional orders. In this study, the encrypted complex data is randomly sampled via compressive sensing (CS) framework by which only 25% of the sparse white noise samples are being reserved to realize decryption with zero or small errors. As a consequence, together with correct phase keys, fractional orders and proper inverse AT operators, lpminimization must be utilized to decrypt the original information. Thus, in addition to the perfect image reconstruction, the proposed cryptosystem provides an additional layer of security to the conventional DRPE system. Both the mathematical and numerical simulations were carried out to verify the feasibility as well as the robustness of the proposed system. The simulation results are presented in order to demonstrate the effectiveness of the proposed system. To the best of our knowledge, this is the first report on integrating CS with encrypted complex samples for information security.

A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC

Using memristor devices as synaptic connections has been suggested with different neural architectures in the literature. Most of the published works focus on simulating some plasticity mechanism for changing memristor conductance. This paper presents a neural architecture of a character recognition neural system using Al/Pr0.7Ca0.3MnO3 (PCMO) memristors. The PCMO memristor has an inhomogeneous barrier at the aluminum and PCMO interface which gives rise to an asymmetrical behavior when moving from high resistance to low resistance and vice versa. This paper details the design and simulations for solving this asymmetrical memristor behavior. Also, a general memory read/write framework is used to describe the running and plasticity of neural systems. The proposed neural system can be produced in hardware using a small 1 K crossbar memristor grid and CMOS neural nodes as presented in the simulation results.

Compressive sensing based robust multispectral double-image encryption

In this study, we investigate the integration of compressive sensing (CS) and photon-counting imaging (PCI) techniques with a ptychography-based optical image encryption system. Primarily, the plaintext real-valued image is optically encrypted and recorded via a classical ptychography technique. Further, the sparse-based representations of the original encrypted complex data can be produced by combining CS and PCI techniques with the primary encrypted image. Such a combination takes an advantage of reduced encrypted samples (i.e., linearly projected random compressive complex samples and photon-counted complex samples) that can be exploited to realize optical decryption, which inherently serves as a secret key (i.e., independent to encryption phase keys) and makes an intruder attack futile. In addition to this, recording fewer encrypted samples provides a substantial bandwidth reduction in online transmission. We demonstrate that the fewer sparse-based complex samples have adequate information to realize decryption. To the best of our knowledge, this is the first report on integrating CS and PCI with conventional ptychography-based optical image encryption.

Neuromorphic Character Recognition System With Two PCMO Memristors as a Synapse

BackgroundCardiac disease is one of the main causes of catastrophic mortality. Therefore, detecting the symptoms of cardiac disease as early as possible is important for increasing the patient’s survival. In this study, a compact and effective architecture for detecting atrial fibrillation (AFib) and myocardial ischemia is proposed. We developed a portable device using this architecture, which allows real-time electrocardiogram (ECG) signal acquisition and analysis for cardiac diseases.MethodsA noisy ECG signal was preprocessed by an analog front-end consisting of analog filters and amplifiers before it was converted into digital data. The analog front-end was minimized to reduce the size of the device and power consumption by implementing some of its functions with digital filters realized in software. With the ECG data, we detected QRS complexes based on wavelet analysis and feature extraction for morphological shape and regularity using an ARM processor. A classifier for cardiac disease was constructed based on features extracted from a training dataset using support vector machines. The classifier then categorized the ECG data into normal beats, AFib, and myocardial ischemia.ResultsA portable ECG device was implemented, and successfully acquired and processed ECG signals. The performance of this device was also verified by comparing the processed ECG data with high-quality ECG data from a public cardiac database. Because of reduced computational complexity, the ARM processor was able to process up to a thousand samples per second, and this allowed real-time acquisition and diagnosis of heart disease. Experimental results for detection of heart disease showed that the device classified AFib and ischemia with a sensitivity of 95.1% and a specificity of 95.9%.ConclusionsCurrent home care and telemedicine systems have a separate device and diagnostic service system, which results in additional time and cost. Our proposed portable ECG device provides captured ECG data and suspected waveform to identify sporadic and chronic events of heart diseases. This device has been built and evaluated for high quality of signals, low computational complexity, and accurate detection.