Indranil Chakraborty

Energy-Efficient Memory Using Magneto-Electric Switching of Ferromagnets

Recent experiments on voltage-driven magneto-electric (ME) switching of ferromagnets has shown potential for future low-energy, high-speed, nonvolatile spintronic memory. In this letter, we first analyze two different ME devices—an ME magnetic-tunnel-junction (ME-MTJ) device and an ME-xnor device—with respect to writability, readability, and switching speed. The basic operational principle of ME devices is the fact that, by applying appropriate voltage pulses on the ME oxides in contact with their respective ferromagnets, a 180° switching of the magnetization direction can be achieved. Our analysis is based on a coupled stochastic magnetization dynamics and electron transport model. Subsequently, we show that the decoupled read/write path of ME-MTJs can be utilized to construct an energy-efficient dual-port memory, which can be instrumental in improving the memory throughput. Furthermore, we also propose a novel nonvolatile, content-addressable, memory that exploits the compact xnor operation enabled by the ME-xnor device.

Toward Fast Neural Computing using All-Photonic Phase Change Spiking Neurons

The rapid growth of brain-inspired computing coupled with the inefficiencies in the CMOS implementations of neuromrphic systems has led to intense exploration of efficient hardware implementations of the functional units of the brain, namely, neurons and synapses. However, efforts have largely been invested in implementations in the electrical domain with potential limitations of switching speed, packing density of large integrated systems and interconnect losses. As an alternative, neuromorphic engineering in the photonic domain has recently gained attention. In this work, we propose a purely photonic operation of an Integrate-and-Fire Spiking neuron, based on the phase change dynamics of Ge2Sb2Te5 (GST) embedded on top of a microring resonator, which alleviates the energy constraints of PCMs in electrical domain. We also show that such a neuron can be potentially integrated with on-chip synapses into an all-Photonic Spiking Neural network inferencing framework which promises to be ultrafast and can potentially offer a large operating bandwidth.

Capacitively Driven Global Interconnect With Energy-Efficient Receiver Based on Magneto-Electric Switching

We propose capacitively driven low-swing global interconnect circuit using a receiver that utilizes magnetoelectric (ME) effect induced magnetization switching to reduce the energy consumption. Capacitively driven wire has recently been shown to be effective in improving the performance of global interconnects. Such techniques can reduce the signal swing in the interconnect by using a capacitive divider network and does not require an additional voltage supply. However, the large reduction in signal swing makes it necessary to use differential signaling and amplification for successful regeneration at the receiver, which add area and static power. ME effect induced magnetization reversal has recently been proposed which shows the possibility of using a low voltage to switch a nanomagnet adjacent to a multi-ferroic oxide. Here, we propose an ME effect based receiver that uses the low voltage at the receiving end of the global wire to switch a nanomagnet. The nanomagnet is also used as the free layer of a magnetic tunnel junction (MTJ), the resistance of which is tuned through the ME effect. This change in MTJ resistance is converted to full swing binary signals by using simple digital components. This process allows capacitive low swing interconnection without differential signaling or amplification, which leads to significant energy efficiency. Our simulation results indicate that for 5-10 mm long global wires in IBM 45 nm technology, capacitive ME design consumes 3x lower energy compared to full-swing CMOS design and 2x lower energy compared to differential amplifier based low-swing capacitive CMOS design.

A non-volatile cascadable magneto-electric material implication logic

Shannons seminal work on Boolean operators — AND, OR, NOT has been the backbone of on-chip digital logic design. This set of the so called basic gates excludes an important mathematical logical operator — the Material Implication (IMP) logic (and its complement (NIMP)), shown in Fig. 1(a). IMP gate along with a NOT/XOR/NIMP gate forms a complete logic basis. Moreover, including IMP as a basic gate along with AND, OR, NOT allows better logic optimization. In this paper, we propose a non-volatile IMP (NIMP) gate that can be seamlessly cascaded to implement complex Boolean functions. Our work differs from previous works as in [1], which used crossbars for implementing IMP logic. Unlike crossbars, our proposed gates can be cascaded and used for standard logic computations or optimization.