Zubair Al Azim

Spin-orbit torque induced spike-timing dependent plasticity

Nanoelectronic devices that mimic the functionality of synapses are a crucial requirement for performing cortical simulations of the brain. In this work, we propose a ferromagnet-heavy metal heterostructure that employs spin-orbit torque to implement spike-timing dependent plasticity. The proposed device offers the advantage of decoupled spike transmission and programming current paths, thereby leading to reliable operation during online learning. Possible arrangement of such devices in a crosspoint architecture can pave the way for ultra-dense neural networks. Simulation studies indicate that the device has the potential of achieving pico-Joule level energy consumption (maximum 2 pJ per synaptic event) which is comparable to the energy consumption for synaptic events in biological synapses.

Laser Induced Magnetization Reversal for Detection in Optical Interconnects

Optical interconnect has emerged as the front-runner to replace electrical interconnect especially for off-chip communication. However, a major drawback with optical interconnects is the need for photodetectors and amplifiers at the receiver, implemented usually by direct bandgap semiconductors and analog CMOS circuits, leading to large energy consumption and slow operating time. In this letter, we propose a new optical interconnect architecture that uses a magnetic tunnel junction (MTJ) at the receiver side that is switched by femtosecond laser pulses. The state of the MTJ can be sensed using simple digital CMOS latches, resulting in significant improvement in energy consumption. Moreover, magnetization in the MTJ can be switched on the picoseconds time-scale and our design can operate at a speed of 5 Gb/s for a single link.

Modeling and Evaluation of Topological Insulator/Ferromagnet Heterostructure-Based Memory

Topological insulators (TIs) are unique materials that have insulating bulk but conducting surface states. In this paper, we propose a simulation framework for TI/ferromagnet (FM) heterostructures that can capture the electronic band structure of a TI while calculating the transport properties. Our model differs from TI/FM models proposed in the literature in a way that it can account for the 3-D band structure of TIs, the effects of exchange coupling and external magnetic field on the band structure. The proposed approach uses 2-D surface Hamiltonian for TIs that includes the quantum confinement effect calculated from a 3-D band diagram. We use this Hamiltonian with self-consistent non-equilibrium Greens functions (NEGF) formalism to determine the charge and spin transport in TI/FM heterostructures. Our calculations agree well with experimental data and capture the unique features of a TI/FM heterostructure, such as the spin Hall angle, spin conductivity, and so on. Next, we incorporate the results into Landau-Lifshitz-Gilbert-Slonczewski formulation to simulate the magnetization dynamics of an FM layer sitting on top of a TI. Finally, we evaluate the performance of three different TI/FM memory structures and show that the TI-based memories can be energy efficient, if the shunting current through the FM layer is reduced.

Spin-Torque Sensors for Energy Efficient High-Speed Long Interconnects

In this paper, we propose a spin-torque (ST)-based sensing scheme that can enable energy efficient multibit long distance interconnect architectures. Current-mode interconnects have recently been proposed to overcome the performance degradations associated with conventional voltage-mode copper interconnects. However, the performance of current-mode interconnects are limited by analog current sensing transceivers and equalization circuits. As a solution, we propose the use of ST-based receivers that use magnetic tunnel junctions and simple digital components for current-to-voltage conversion, and do not require analog transceivers. We incorporate spin-Hall metal in our design to achieve high-speed sensing. We show both single and multibit operations that reveal major benefits at higher speeds. Our simulation results show that the proposed technique consumes only 3.93-4.72 fJ/b/mm energy while operating at 1-2 Gb/s, which is considerably better than existing charge-based interconnects. In addition, voltage-controlled magnetic anisotropy (VCMA) can reduce the required current at the sensor. With the inclusion of VCMA, the energy consumption can be further reduced to 2.02-4.02 fJ/b/mm.

Buffered Spin-Torque Sensors for Minimizing Delay and Energy Consumption in Global Interconnects

We propose a low-voltage, low-current interconnect architecture using buffered/pipelined spin-torque (ST) sensors to optimize the overall delay and energy consumption. Conventional techniques for reducing energy consumption on long interconnects involve low voltage swings on interconnects or current-mode interconnects. However, such techniques require power-consuming voltage converters or trans-impedance amplifiers at the receivers. ST-sensor-based receivers have recently been introduced that can operate without analog components at the receiver. As a result, the energy consumption is lower compared to existing techniques. However, the delay can be relatively high in these networks for long Cu-lines since these methods do not accommodate conventional buffering schemes for delay minimization. Here, we propose the use of ST buffers in the line in addition to ST-sensing at the receiver. The buffers and sensors used in our design consist of a magnetic strip of two magnetic domains separated by a domain wall. The domain wall can be moved by a current flowing through an adjacent spin-Hall metal which leads to a change in the resistance of the receiver. This resistance change is easily sensed using simple CMOS components. With the introduction of buffering for ST-sensor interconnects, the proposed method can be highly efficient in optimizing the energy-delay performance for long, global on-chip or off-chip lines. Our simulation results indicate that for a 10 mm line in 45 nm CMOS technology, the energy consumption with ST-sensing is about 2 percent that of full-swing, and about 4 percent that of low-swing, CMOS interconnects. Moreover, the delay is much lower than low-swing, and comparable to full-swing, CMOS designs.

Skyrmion Sensor-Based Low-Power Global Interconnects

In this paper, we propose the use of magnetic skyrmion sensors for low-voltage, low-current global interconnects. Magnetic skyrmions have shown great potential for low-power circuit applications, since skyrmions can be generated and moved by remarkably low-current pulses. We propose the use of skyrmion-based current sensors at the receiver that allows low-current signal transmission through the line. The proposed skyrmion sensor consists of a magnetic nanotrack on top of a spin-Hall metal (SHM). The skyrmion is nucleated in the nanotrack by using spin-polarized current and, subsequently, moved along the nanotrack by using a charge current through the SHM. This charge current is the input current from a global interconnect line, which moves the skyrmion depending on the logic input to the line. The resistance of a magnetic tunnel junction (MTJ) at the receiver is based on the movement/location of the skyrmion. This resistance change is sensed using a reference MTJ and a simple complementary metal-oxide-semiconductor (CMOS) inverter. Such a receiver configuration acts as a built-in latch, and hence, expensive voltage converters or transimpedance amplifiers can be avoided, which are the bottlenecks in a conventional low-power interconnect design. Our simulation results indicate that for a 10 mm Cu-line in 45 nm CMOS technology, the energy consumption with skyrmion-based sensing is ~50× lower compared with full swing and ~25× lower compared with low-swing CMOS interconnect.

Capacitively Driven Global Interconnect With Energy-Efficient Receiver Based on Magneto-Electric Switching

We propose capacitively driven low-swing global interconnect circuit using a receiver that utilizes magnetoelectric (ME) effect induced magnetization switching to reduce the energy consumption. Capacitively driven wire has recently been shown to be effective in improving the performance of global interconnects. Such techniques can reduce the signal swing in the interconnect by using a capacitive divider network and does not require an additional voltage supply. However, the large reduction in signal swing makes it necessary to use differential signaling and amplification for successful regeneration at the receiver, which add area and static power. ME effect induced magnetization reversal has recently been proposed which shows the possibility of using a low voltage to switch a nanomagnet adjacent to a multi-ferroic oxide. Here, we propose an ME effect based receiver that uses the low voltage at the receiving end of the global wire to switch a nanomagnet. The nanomagnet is also used as the free layer of a magnetic tunnel junction (MTJ), the resistance of which is tuned through the ME effect. This change in MTJ resistance is converted to full swing binary signals by using simple digital components. This process allows capacitive low swing interconnection without differential signaling or amplification, which leads to significant energy efficiency. Our simulation results indicate that for 5-10 mm long global wires in IBM 45 nm technology, capacitive ME design consumes 3x lower energy compared to full-swing CMOS design and 2x lower energy compared to differential amplifier based low-swing capacitive CMOS design.

Spin-torque sensors with differential signaling for fast and energy efficient global interconnects

We propose a hybrid global interconnect that combines Spin-Torque (ST) sensors with differential amplifiers to greatly reduce the overall power consumption while minimizing the delay along the line. ST-sensor based interconnects have recently been proposed that show significant energy efficiency compared to conventional full swing CMOS interconnects. However, the latency of ST-sensor interconnects can be rather high due to inefficient signal regeneration along the line. As a solution, we propose the use of differential amplifiers as repeaters along with ST-sensor as receiver to speed up the interconnect delay. Moreover, the introduction of differential signaling greatly increases the robustness of the design against noise and variations. Our simulation results indicate that for a 10 mm line in 45 mm CMOS technology, the energy consumption with hybrid ST-sensor interconnect is ∼5× lower compared to full-swing CMOS interconnect while operating at similar speed. Moreover, the energy consumption is ∼2× lower compared to low-swing CMOS interconnect, in addition to significant improvement in latency.