Ing-Jer Huang

A retargetable embedded in-circuit emulation module for microprocessors

Our objective is to develop a feasible, low-cost, retargetable embedded ICE-with as few modifications to the standard as possible-that can be easily integrated with microprocessor cores at the register-transfer level. This module, which can be embedded with a microprocessor core, makes real-time, online debugging at full speed possible with a minor gate-count overhead.

A Low Cost Tile-based 3D Graphics Full Pipeline with Real-time Performance Monitoring Support for OpenGL ES in Consumer Electronics

This paper presents a 3D graphics engine which is specifically designed to minimize the hardware cost while providing sufficient computing capability for consumer electronics with small to medium screen sizes (up to 800times600) such as digital television. The presented 3D engine consists of a fixed full 3D graphics pipeline for both geometry and rendering operation. This engine provides a standard AHB interface that makes it easily to be integrated into an AMBA-based SoC. The development of the 3D engine has gone through a rigorous design process: starting from system modeling (using System-C), RTL implementation, hardware/software co-simulation and FPGA verification to test chip fabrication. This 3D engine provides 3.3 M vertices/s and 278 Mpixels/s in maximum performance at 139 MHz using 0.18 silicon technology with 987 K gates that is sufficient for most applications for digital television. At the same time, a complete OpenGL-ES 1.1 API, windowing system, Linux operating system, device driver and a 3D performance monitoring tool have been developed for our 3D engine. This performance monitoring tool provides run-time performance information include frame rate, triangle rate, pixel rate, involved OpenGL function list, function counts, memory utilization and etc. Moreover, a built-in real-time AHB bus tracer is also provided to monitor the bus activities of the 3D engine and other components on the system bus. The bus tracer captures on-chip bus signals at ether cycle accurate or transaction levels and applies real-time compression to both levels of signals. With the performance monitoring tool and the bus tracer, the 3D application developer can easily analyze the communication of the components and fine tune the 3D application to optimize the entire SoC system performance and to satisfy performance/cost constrains on consumer electronics. Both of the hardware and software have been carefully verified and demonstrated on FPGA using ARM versatile SoC develop board.

An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC

This paper proposes a multiresolution AHB on-chip bus tracer named SYS-HMRBT (aHb multiresolution bus tracer) for versatile system-on-chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of needs. In addition, it allows users to switch the trace resolution dynamically so that appropriate resolution levels can be applied to different segments of the trace. On the other hand, SYS-HMRBT supports tracing after/before an event triggering, named post-triggering trace/pre-triggering trace, respectively. SYS-HMRBT runs at 500 MHz and costs 42 K gates in TSMC 0.13-m technology, indicating that it is capable of real time tracing and is very small in modern SoCs. Experiments show that the bus tracer achieves very good compression ratios of 79%-96%, depending on the selected resolution mode. As a case study, it has been integrated into a 3-D graphics SoC to facilitate the debugging and monitoring of the system behaviors. The SoC has been successfully verified both in field-programmable gate array and a test chip.

Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors

In-circuit emulators have become part of the permanent structure of microprocessor cores to support on-chip test and debug activities in highly integrated environments such as SoCs. However, ICE design styles and operation principles are quite diverse. This article presents a taxonomy based on the notions of foreground and background operations and hardwaresoftware implementation alternatives to organize existing in-circuit emulation approaches.

A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization

Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The compression algorithm must be simple for hardware implementation; a common method is to store only the difference between the previous value and the current one. Such differential compression has trouble with the circular buffer that is needed for recording continuous traces. Previous solutions are complex and waste memory. By a transformation that expresses differential compression in reverse form, we derive a new solution that is simpler than previous methods and does not waste memory. Our algorithm is based on an innovative reverse-encoding scheme by reversing the order of the datum being encoded and the datum being referred. This algorithm has been successfully implemented in a real-time on-chip advanced high-performance bus tracer and has been embedded in a 3-D graphics system-on-a-chip as an application example. The bus tracer costs only 44 K gates and runs at 500 MHz in TSMC 0.13-¿m technology. Experiments have shown that our bus tracer achieves 100% circular-buffer utilization and captures 4.86 times trace depths as compared with a conventional industrial approach.

A trace-capable instruction cache for cost efficient real-time program trace compression in SoC

This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time program trace compressor. This goal is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. The trace compression works in both the bypass mode and the online mode. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource. The RTL implementation of a 4KB trace-capable instruction cache, a 4KB data cache and an academic ARM7 processor core has been accomplished. The experiments show that the cache achieves average compression ratio of 90% with a very small hardware overhead of 3652 gates. In addition, the trace support circuit does not impact the global critical path. Therefore, the proposed approach is highly feasible on-chip debugging/monitoring solution for SoCs, even for cost sensitive ones such as consumer electronics.

Reusable embedded in-circuit emulator

In this paper, we o introduce the Reusable Embedded In-Circuit Emulator (EICE) and Reusable EICE development system. The main function in EICE we design are testing and debugging. The architecture of EICE is reusable and based on IEEE 1149.1 boundary scan architecture. The EICE development system can help EICE to reduce developing time while developing a microcontroller/microprocessor. We implemented EICE by ASIC and FPGA way and the development system had been demonstrated in two microcontroller.

A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC

This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real-time program trace compressor, named trace-capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource and power consumption. The TC-cache can be configured to work simultaneously as the instruction cache and the trace compressor, named the online mode, or exclusively as the trace compressor, named the bypass mode. The RTL implementation of a 4 KB trace-capable instruction cache, a 4 KB data cache, and an academic ARM processor core has been accomplished. The experiments show that the TC-cache achieves average compression ratio of 90 percent with a very small hardware overhead of 3,652 gates (1.1 percent). It takes only 0.2 percent additional system power for the online mode operation. In addition, the trace support circuit does not impair the global critical path. Therefore, the proposed approach is a highly feasible on-chip debugging/monitoring solution for SoCs, even for cost-sensitive ones such as consumer electronics. Furthermore, the same concept can be applied to the data cache to compress the data address trace as well.

An efficient HW/SW integrated verification methodology for 3D Graphics SoC development

This paper proposes an efficient HW/SW integrated verification methodology for 3D Graphics (3DG) acceleration on SoC development. The proposed methodology is built for verifying 3DG SoC with FPGA emulation and contains a GUI analyzing tool for displaying emulation results and assisting HW/SW debugging automatically. With the verification methodology, designers can detect unobvious bugs from HW and SW modules individually and shorten the verification time during SoC integration. In this paper, we will introduce the implemented environment of 3DG SoC and elucidate significance and necessary of proposed method. For the convenience of verification, the analyzing tool that we have developed contains the functions of displaying frame results, comparing different benchmarks, recording FPGA emulation, detecting pixel color, and analyzing bug statistics. As a result, this verification methodology with analyzing tool will help designers to easily verify the complicated 3DG SoC.

A dynamic PCM codec selector for different working environments

Quality of transmission is very important in digital communication. The BER (bit error rate) of a PCM encoding method may be varied according to different working condition or different signal source. Theoretically, the BER of encoding method can be estimated mathematically. The BER is generally assumed as a constant value. The BER, however, is not deterministic in real world. In this paper, a Dynamic PCM Selector that can dynamically select an optimal PCM codec module is proposed. The system can dynamically switch to the encoding mode with possible lowest BER, according to the current type of the transmission. By way of this design, it can greatly reduce the overheads of the error correction process.