Hsin-Ming Chen

A New CMOS Logic Anti-Fuse Cell with Programmable Contact

A new fully CMOS process compatible anti-fuse device with programmable contact has been developed for advanced programmable logic applications. This anti-fuse processed by pure logic process and decoupled with transistor gate oxide has a highly stable and extremely wide on/off window. It exhibits superior disturb immunity in program and read operations. The device additionally provides the capability to adapt multiple programmable contacts for the needs of elevated data writing and reading performance. This novel anti-fuse cell is a very promising programmable logic solution with fully CMOS logic compatible process below 0.13¿m node.

A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process

A new 45 nm multiple time programming (MTP) cell with self-aligned nitride storage node has been proposed for logic NVM applications. The CMOS fully logic compatible cell has been successfully demonstrated in 45 nm CMOS technology with an ultra small cell size of 0.14 mum2. This cell adapting source side injection programming scheme has a wide on/off window and superior program efficiency. And it also exhibits excellent data retention capability even when logic gate oxide is less than 20 Aring with 45 nm gate length. This new cell provides a promising solution for logic NVM beyond 90 nm node.

45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process

A new gateless anti-fuse cell with 45 nm CMOS fully compatible process has been developed for advanced programmable logic applications. This gateless anti-fuse cell processed by pure logic process and decoupled with logic gate oxide has a highly stable and five orders of on/off current window. It also exhibits superior program performance by only 5 V operation with no more than 10 muA programming current. This new nitride gateless anti-fuse cell is a very promising logic OTP solution with fully CMOS compatible process below 90 nm node.

A Novel 2-Bit/Cell p-Channel Logic Programmable Cell With Pure 90-nm CMOS Technology

A new p-channel nitride-based one-time programmable (OTP) memory was developed for advanced-logic nonvolatile-memory (NVM) applications. A 0.296-mum2/bit (~35 F2) OTP cell, i.e., 0.592 mum2/cell, with a self-aligned nitride storage node was fabricated using standard 90-nm CMOS processes and is fully independent of gate oxide for high scalability. Additionally, the ultrahigh-density OTP cell exhibits excellent retention, immunity against disturbance, and a wide on/off window under the band-to-band hot electron programming. In summary, the new p-channel OTP cell is a very promising solution for use in high-density logic NVM applications beyond the 90-nm technology node.

Performance and Reliability Trade-off of Large-Tilted-Angle Implant P-Pocket on Stacked-Gate Memory Devices

In this paper, the effects of large-tilted-angle p-pocket (LAP) implantation on the performance and reliability of stacked-gate memory cell are investigated. The utilization of LAP process achieves the improved programming efficiency and reduced punchthrough susceptibility. The 45° LAP cell featuring a fastest programming speed, however, would not be desirable due to the seriously aggravated read current degradation, drain/read disturbance, and early snap-back breakdown. The cells with 0° and 30° tilted angle are the feasible cells with the moderate programming performance and acceptable reliability constraints. Furthermore, the 0° LAP cell is preferred for the fact that it exhibits the desirable read current than that in 30° cell. Based on the cell performance and reliability consideration, the 0° p-pocket implanted cell is the optimal angle among 0°, 30° and 45° for the future scaling of stacked-gate memory cell.