Ioannis Kouretas

Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters

This paper presents techniques for low-power addition/subtraction in the logarithmic number system (LNS) and quantifies their impact on digital filter VLSI implementation. The impact of partitioning the look-up tables required for LNS addition/subtraction on complexity, performance, and power dissipation of the corresponding circuits is quantified. Two design parameters are exploited to minimize complexity, namely the LNS base and the organization of the LNS word. A roundoff noise model is used to demonstrate the impact of base and word length on the signal-to-noise ratio of the output of finite impulse response (FIR) filters. In addition, techniques for the low-power implementation of an LNS multiply accumulate (MAC) units are investigated. Furthermore, it is shown that the proposed techniques can be extended to cotransformation-based circuits that employ interpolators. The results are demonstrated by evaluating the power dissipation, complexity and performance of several FIR filter configurations comprising one, two or four MAC units. Simulations of placed and routed VLSI LNS-based digital filters using a 90-nm 1.0 V CMOS standard-cell library reveal that significant power dissipation savings are possible by using optimized LNS circuits at no performance penalty, when compared to linear fixed-point twos-complement equivalents.

Residue arithmetic for variation-tolerant design of multiply-add units

This paper investigates the residue arithmetic as a solution for the design of variation-tolerant circuits. Motivated by the modular organization of residue processors, we comparatively study the sensitivity of residue arithmetic-based and binary processors to delay variations, and in particular the impact of delay variations onto the maximum critical path. Experiments are performed on two multiply-add (MAC) circuits based on residue and binary arithmetic. Results reveal that residue arithmetic-based circuits are up to 94% less sensitive to delay variation than binary circuits, thus leading to increased timing yield.

A Low-Complexity High-Radix RNS Multiplier

A graph-based technique is introduced for the design of a class of residue arithmetic multipliers, as well as a family of new high-radix digit adders. A proposed design technique derives simple high-radix modulo-r n multipliers by optimally selecting among the variety of introduced digit adders the ones that compose a minimal-area multiplier. The proposed technique minimizes multiplier complexity by selecting digit adders that observe the constraints imposed on the maximum values of the various intermediate digits. The proposed technique leads to significant area and time improvements over previously published architectures for practical modulus cases.

Low-power digital filtering based on the logarithmic number system

This paper investigates the use of the Logarithmic Number System (LNS) as a low-power design technique for signal processing applications. In particular we focus on power reductions in implementations of FIR and IIR filters. It is shown that LNS requires a reduced word length compared to linear representations for cases of practical interest. Synthesis of circuits that perform basic arithmetic operations using a 0.18µm 1.8V CMOS standard-cell library, reveal that power dissipation savings more than 60% in some cases are possible.

Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation

In this paper the utilization of Residue Number System (RNS) is investigated as a tool for variation-tolerant design. In particular circuits using various RNS bases are compared to the equivalent binary structures in terms of their sensitivity to the variation of process parameters. Furthermore, RNS advantages are quantitatively illustrated by considering a timing model with two non-gaussian distributions. It is shown that for bases where all moduli channels are candidates to contain the critical path of the RNS circuit, the delay variation is significantly reduced when compared to the equivalent binary structures.

Low-power logarithmic number system addition/subtraction and their impact on digital filters

This paper presents techniques for low-power addition/subtraction in the logarithmic number system (LNS) and quantifies their impact on digital filter VLSI implementation. The impact of partitioning the look-up tables required for LNS addition/subtraction on complexity, performance, and power dissipation of the corresponding circuits is quantified. Two design parameters are exploited to minimize complexity, namely the LNS base and the organization of the LNS word. A roundoff noise model is used to demonstrate the impact of base and word length on the signal-to-noise ratio of the output of finite impulse response (FIR) filters. In addition, techniques for the low-power implementation of an LNS multiply accumulate (MAC) units are investigated. Furthermore, it is shown that the proposed techniques can be extended to cotransformation-based circuits that employ interpolators. The results are demonstrated by evaluating the power dissipation, complexity and performance of several FIR filter configurations comprising one, two or four MAC units. Simulations of placed and routed VLSI LNS-based digital filters using a 90-nm 1.0 V CMOS standard-cell library reveal that significant power dissipation savings are possible by using optimized LNS circuits at no performance penalty, when compared to linear fixed-point twos-complement equivalents.

Towards a Quaternion Complex Logarithmic Number System

The well-known generalization of real to complex arithmetic (two reals) extends further to more obscure quaternion arithmetic (four reals), which has applications in signal processing, aerospace, graphics and virtual reality. Quaternion multiplication implements 3D rotation, but is expensive (usually 16 floating-point multiplications and 12 additions). This paper proposes an alternative quaternion representation using logarithms to reduce multiplication cost. The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division in embedded and FPGA-based systems. Recent advances in the Complex LNS (CLNS) [5] have made fast log-polar complex representation affordable. Although the quaternion logarithm function is also well-defined, it is not useful to simplify multiplication (in the same way real and complex logarithms are) because quaternion multiplication is not commutative but quaternion addition is. To overcome this, we propose a novel Quaternion Complex (QCLNS) representation using a pair of CLNS numbers. This representation implements quaternion multiplication using only the theoretical minimum [11], [15] of 8 LNS multipliers (i.e., fixed-point adders) and two CLNS adders. Because CLNS numbers are more compact than ordinary rectangular complex representation, single-precision QCLNS occupies 10.9 percent less memory than conventional quaternion representation. Extrapolating conventional LNS and floating-point synthesis data from Fu et al. [12], QCLNS saves on average 10 percent of FPGA resources for precisions between 13 and 45 bits.

Delay-variation-tolerant FIR filter architectures based on the Residue Number System

This paper investigates the use of the Residue Number System (RNS) in the hardware design of VLSI FIR filters implemented in nano-scale technologies prone to process variation effects. It is here shown that the RNS substantially reduces the filter sensitivity to delay variations, when compared to digital filter designs that use conventional positional number systems, such as the widely-used twos-complement representation. The inherent tolerance of the introduced RNS architectures to the delay variations, is here shown to allow to circumvent the use of large design parameter margins. Therefore, we demonstrate that the use of RNS can achieve a high timing yield without resorting to costly over-design, which may unnecessarily increase system complexity. The particular benefit comes in addition to area, time and power benefits achieved due to the use of the RNS. The quantitative digital filter design space exploration reported in the paper takes into consideration the filter order as well as criteria related to the filter output signal quality such as the signal-to-noise ratio (SNR) and it demonstrates that the proposed architectures offer effective solutions for hardware design using modern and future nano-scale processes, for filter cases of practical interest.

Residue arithmetic bases for reducing delay variation

In this paper the utilization of Residue Number System (RNS) is investigated as a tool for variation-tolerant design. In particular circuits using various RNS bases are compared in terms of their sensitivity to the variation of process parameters. Furthermore, RNS advantages are quantitatively illustrated by considering a timing model. It is shown that for bases where all moduli channels are candidates to contain the critical path of the RNS circuit, the delay variation is reduced upto 86% when compared to the equivalent binary structures.

RNS multi-voltage low-power multiply-add unit

In this paper an efficient way to exploit multi-Vdd standard-cell libraries is quantitatively investigated as a means to reduce power consumption of multiply-add units. It is shown that multi-Vdd library-based design is suitable for RNS systems due to their inherent modular organization. In particular the paths defined by the isolated moduli channels are clearly distinguished and the designer can easily and efficiently determine high- and low-voltage areas in the design. A five-moduli RNS system has been implemented including RNS-to-Binary and Binary-to-RNS converters.