Mark G. Arnold

A System-on-a-Chip Implementation for Embedded Real-Time Model Predictive Control

This paper presents a hardware architecture for embedded real-time model predictive control (MPC). The computational cost of an MPC problem, which relies on the solution of an optimization problem at every time step, is dominated by operations on real matrices. In order to design an efficient and low-cost application-specific processor, we analyze the computational cost of MPC, and we propose a limited-resource host processor to be connected with an application-specific matrix coprocessor. The coprocessor uses a 16-b logarithmic number system arithmetic unit, which is designed using cotransformation, to carry out the required arithmetic operations. The proposed architecture is implemented by means of a hardware description language and then prototyped and emulated on a field-programmable gate array. Results on computation time and architecture area are presented and analyzed, and the functionality of the proposed architecture is verified using two case studies: a linear problem of a rotating antenna and a nonlinear glucose-regulation problem. The proposed MPC architecture yields a small-in-size and energy-efficient implementation that is capable of solving the aforementioned problems on the order of milliseconds, and we compare its performance and area requirements with other MPC designs that have appeared in the literature.

A co-processor FPGA platform for the implementation of real-time model predictive control

In order to effectively control nonlinear and multivariable models, and to incorporate constraints on system states, inputs and outputs (bounds, rate of change), a suitable (sometimes necessary) controller is model predictive control (MPC). MPC is an optimization-based control scheme that requires abundant matrix operations for the calculation of the optimal control moves. In this work we propose a mixed software and hardware embedded MPC implementation. Using a codesign step and based on profiling results, we decompose the optimization algorithm into two parts: one that fits into a host processor and one that fits into a custom made unit that performs the computationally demanding arithmetic operations. The profiling results and information on the co-processor design are provided

Redundant logarithmic arithmetic

A number system that offers advantages in some situations over conventional floating point and sign/logarithmic number systems is described. Redundant logarithmic arithmetic, like conventional logarithmic arithmetic, relies on table lookups to make the arithmetic unit simpler than an equivalent floating point unit. The cost of 32 bit subtraction in a redundant logarithmic number system is lower than previously published logarithmic subtraction methods. The total memory requirement for a 29-bit redundant logarithmic unit is 16 K words compared to 22 K words by the best previously published conventional sign logarithm unit, assuming similar addition techniques are employed. A redundant logarithmic number system can be implemented with online arithmetic, which would be impractical for a conventional sign logarithm number system. The disadvantages of redundant arithmetic are typical of redundant number systems. First, the redundancy doubles the storage requirements for data values. Second, the representation can become ill-conditioned, especially as a result of iterated multiplications. Third, division and square root operations are more difficult to implement in redundant logarithmic arithmetic. >

Applying features of IEEE 754 to sign/logarithm arithmetic

Various features found in standard floating point arithmetic (IEEE 754) are examined in light of their appropriateness for sign/logarithm arithmetic. The emphasis is on a 32-b word size comparable to IEEE 754 single precision, although other word sizes are possible. A multilayer sign/logarithm format is considered. The lowest layer, similar to previous implementations, would provide only normalized representations but would not provide representations for zero, denormalized values, infinities, and NaNs. The highest layer would provide most of the features found in IEEE 754, including zeros, denormalized values, infinities, and NaNs. Novel algorithms for implementing logarithmic denormalized arithmetic are presented. Simulation results show that the error characteristics of the proposed logarithmic denormalized arithmetic algorithms are similar to those of the denormalized floating point arithmetic in IEEE 754. >

Arithmetic co-transformations in the real and complex logarithmic number systems

The real logarithmic number system, which represents a value with a sign bit and a quantized logarithm, can be generalized to create the complex logarithmic number system, which replaces the sign bit with a quantized angle in a log/polar coordinate system. Although multiplication and related operations are easy in both real and complex systems, addition and subtraction are hard, especially when interpolation is used to implement the system. Both real and complex logarithmic arithmetic benefit from the use of co-transformation, which converts an addition or subtraction from a region where interpolation is expensive to a region where it is easier. Two co-transformations that accomplish this goal are introduced. The first is an approximation based on real analysis of the subtraction logarithm. The second is based on simple algebra that applies for both real and complex values and that works for both addition and subtraction.

Hardware-based support vector machine classification in logarithmic number systems

Support vector machines are emerging as a powerful machine-learning tool. Logarithmic number systems (LNS) utilize the property of logarithmic compression for numerical operations. We present an implementation of a digital support vector machine (SVM) classifier using LNS in which, when compared with other implementations, considerable hardware savings are achieved with no significant loss in classification accuracy.

Unrestricted faithful rounding is good enough for some LNS applications

We propose to relax the restricted form of faithful rounding used in prior 32 bit logarithmic number system (LNS) implementations. Unrestricted faithful rounding yields three- to six-fold savings in VLSI ROM size (or four- to six-fold savings in FPGA table size) with only a modest increase in error. This can be acceptable for the DSP and multimedia applications in which the non-standard LNS is a candidate for adoption. Such applications are cost sensitive, and the tremendous cost reduction of the LNS model proposed should argue very favourably for its adoption.

LNS architectures for embedded model predictive control processors

This paper presents a research on arithmetic units targeted to implement model predictive control (MPC) in a custom embedded processor. A novel hardware implementation of cotransformation for the calculation of addition and subtraction in the Logarithmic Number System (LNS) is proposed. This architecture provides a small ROM-less adder/subtracter, with longer operation latency than other LNS techniques, but easily pipelineable. These characteristics make it very adequate for implementing the datapath of custom MPC embeddable microprocessors. A review of the arithmetic customization process is presented, including: an analysis of the finite precision problem, modifications to the standard MPC algorithm that simplify embedding the application, and the reasons that suggest better performance of LNS over standard floating-point (FP) architectures. The proposed arithmetic unit architecture for 16-bit LNS is fully synthesized for ASIC, and compared with an equivalent FP implementation. Area and clock cycle estimates are compared. Finally, considerations on low-precision implementations of LNS arithmetic units are provided, and an embedded-ROM implementation of addition/subtraction in LNS is proposed and analyzed.

Reduced power consumption for MPEG decoding with LNS

By reducing the accuracy of the logarithmic number system (LNS) it is possible to achieve lower power consumption for multimedia applications, such as MPEG, without significantly lowering the visual quality of the output. An LNS wordsize of 8 to 10 bits produces a comparable MPEG output as a fixed-point wordsize of 14 to 16 bits. The switching activity of an LNS ALU that computes the inverse discrete cosine transform (IDCT) is one quarter that of fixed point, implying lower power consumption. By skipping inputs that are zero (which MPEG can do naturally with its run-length coding and zigzag ordering) the switching activity of LNS MPEG becomes one-tenth that of fixed point, in contrast to the minimal impact zero skipping has on fixed-point power consumption.

Improved accuracy for logarithmic addition in DSP applications

Logarithmic number systems are an attractive method of implementing high-speed digital signal-processing systems with a word size of about 14 bits. Larger word sizes pose problems because of the address limitations of the ROMs needed for logarithmic addition. M.G. Arnold (1982) gave several interpolation techniques that can double the precision, but these techniques require the use of a fixed-point multiplier. F.J. Taylor (1983) proposed a modified linear interpolation that could increase the precision by about four bits without using a multiplier. It is shown that an improvement can be made in Taylors technique by choosing a different constant. Also, by combining one of Arnolds techniques with a variant of Taylors modification, precision similar to that of Taylors design can be obtained using a simpler circuit.<<ETX>>