Ireneusz Brzozowski

Minimisation of power consumption in digital integrated circuits by reduction of switching activity

The authors aim at directing attention on the problem of minimisation power consumption in combined digital integrated circuits by way of minimising the total number of switchings of all the gates in the circuit, which perform the required logical function. An attempt of providing this minimisation at the stage of the circuit logical synthesis is a novelty.

Calculation methods of new circuit activity measure for low power modeling

Calculation procedures for the gate driving way probability - the new measure of a circuit activity, developed for low power modeling - are presented in this paper. The new model of power dissipation, using the measure, has improved estimation accuracy. Moreover, it allows developing of new methods for low power design. The gate driving way can be easy calculated using logic simulations, but it is time-consuming method. So, the authors propose efficient and fast calculation procedures. The versatile algorithm for any circuit has been developed as well as very fast one for two-level circuits only. Results of new algorithms using were compared for a set of MCNC benchmark circuits.

Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation

Accurate analysis of CMOS gate power dissipation shows that amount of consumed energy depends on a reason of the gate switching. Number of activated inputs and type of applied signals have an influence on dynamic power dissipation of the gate due to dynamic reconfiguration of internal gate parasitic capacitors. Therefore, authors propose new modeling of dynamic power dissipation in static CMOS gates. Accurate modeling of dynamic power dissipation needs to take into consideration changes of all input signals. So, authors introduce new measure of digital circuit activity - gate driving way - for precise modeling of power dissipation. Based on conclusions flowing from the model analysis, authors propose method for two-level low-power circuits design.

Designing of low-power data oriented adders

Abstract The paper presents an idea of designing of low-power adders addressed to specific data processing. Mainly, the idea consists in proper choosing of 1-bit full adder cells for given probability of summed data, to obtain reduction in consumed power. Additionally different structures of the cells can be used, in one design, if it leads to reduction of power dissipation. To proper choice of structures of 1-bit full adders theirs energy characteristic versus summed data is needed. So, at the beginning we present results of assessment of a few 1-bit adder cells selected from literature and designed in UMC180 CMOS technology. The extended model of power consumption, taking into consideration input vector changes, was used, giving more accurate values than traditional model based on switching activity only. Thanks to the use of this model, obtained results allow detailed analysis of 1-bit adders on account of the using them in designing of low-power multi-bit adders summing specific data. Based on the results of analyses and given characteristic of summed data, appropriate full adder cells can be chosen to the final design of low-power data oriented adder. In specific case, cells which are made in different techniques can be used in multi-bit adder. A few examples are shown at the end of the paper.

Power dissipation reduction during synthesis of two-level logic based on probability of input vectors changes

Detailed analysis of CMOS gate behaviour shows that a gate load and input capacitance depends on number of their activated inputs and kind of applied signals i.e. steady state, edge. And in consequence it has an influence on power dissipation. So a reason of the gate switching can be called as the gate driving way. Based on the probability of the gate driving way and associated portion of dissipated energy more accurate model of power dissipation for CMOS gates and circuits is presented. Example of circuits synthesis show power reduction possibilities during design of two-level logic circuits based on information about primary input vector changes – a new circuit activity measure.

Energy consumption minimisation with new synthesis method

The paper deals with a logic synthesis method, which leads to minimisation of energy consumed by integrated digital circuits thanks to the decrease of switching activity. As a consequence, less complicated, smaller, more reliable and faster digital circuits can be obtained. The hypothetical circuits were proposed, simulated, fabricated in CMOS technology and tested. The examples show that we are able to save significant amounts of energy.

Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm

In the paper we propose a novel architecture and implementation of 10-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-BD Double-sided (LBDD) algorithm has been used to calculate the DPWM signals of the 10-bit resolution hybrid DPWM for a Class-D digital audio amplifier. Noise-shaping process is used to support high fidelity with feasible values of time resolution. The proposed DPWM circuit is composed of two 6-bit counters and one Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay elements has been presented elsewhere [12]. The proposed 10-bit DPWM circuit, at switching frequency of 352.8 kHz, clock frequency of 45 MHz allows to attain SNR of 120 dB and THD of the output signal less than 0,1% within the audio baseband and modulation index of 0.98. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for one CMOS process are presented.

The miller effect in digital CMOS gates and power consumption analysis

This paper deals with the Miller Effect occurrence in standard CMOS gates and possibility to take it into considerations during power dissipation analysis. Internal capacitances occurring in MOS transistors give the effect of capacitive coupling between input and output of the gate. It seems that the Miller theorem can be applied in a simplified approach to the analysis of energy and time in static CMOS gates. The main purpose of this paper is to discuss whether the Miller theorem can be effectively used in the analysis of energy and time in CMOS gates. What is the accuracy of such approach and what are the limitations? Theoretical considerations are supplemented by simulations.

Breath sensor based on conductive foam: Idea, construction, and characterisation

This paper deals with breath sensor constructed based on conductive, polyurethane foam, which is usually used for storage of electronics devices. A piece of the foam with especially prepared terminals is placed under tight T-shirt at the chest of a monitored person. The paper presents the idea of the sensor, investigation on its construction and problems being faced with. Parameters assessment processes and results are described too, so finally well characterized electronics component, ready to use, is presented. Some examples of use of the sensor are presented at the end of the paper.

Extraction of temperature dependent parameters for an electrothermal model of thermoelectric energy harvester

A method and procedures have been developed for extraction of temperature dependent parameters of a thermoelectric energy harvester. Temperature functions of Seebeck coefficient S, electrical resistance R, and thermal conductance K were carried out. They are all indispensable for accurate simulation of complex electro-thermal processes associated with conversion of small pieces of free heat energy. The paper discusses the modelling of a single tiny thermoelectric generator with high-density pellets placement. It is intended to be used as a single building block in a wearable thermoelectric matrix for harvesting and conversion of human warmth to electricity.