Andrzej Kos

Minimisation of power consumption in digital integrated circuits by reduction of switching activity

The authors aim at directing attention on the problem of minimisation power consumption in combined digital integrated circuits by way of minimising the total number of switchings of all the gates in the circuit, which perform the required logical function. An attempt of providing this minimisation at the stage of the circuit logical synthesis is a novelty.

Temperature influence on power consumption and time delay

Both the energy consumption and the propagation time delay are very critical parameters of contemporary integrated circuits. It is obvious that a circuit should consume energy as small as possible and ought to work with maximum speed and efficiency. However, these parameters are dependent on temperature, which can change with both external (e.g. high surrounding temperature) and internal (e.g. power dissipated in the circuit) conditions. The article presents the temperature influence on energy consumption and propagation time delay of CMOS ASIC circuits at the example of AMI Semiconductor 0.7 /spl mu/ CMOS C07MD technology (former Alcatel MIETEC CMOS 0.7 /spl mu/m-C07MA-C07MD). The gate was tested under the two conditions: controlled by ideal trapezoid pulse signal, and controlled by real output signal that came from previous gate.

Analysis And Design Of Ptat Temperature Sensor In Digital CMOS VLSI Circuits

The paper presents theoretical analyses, simulations and design of a PTAT (proportional to absolute temperature) temperature sensor that is based on the vertical PNP structure and dedicated to CMOS VLSI circuits. Performed considerations take into account specific properties of materials that forms electronic elements. The electrothermal simulations are performed in order to verify the unwanted self-heating effect of the sensor

Calculation methods of new circuit activity measure for low power modeling

Calculation procedures for the gate driving way probability - the new measure of a circuit activity, developed for low power modeling - are presented in this paper. The new model of power dissipation, using the measure, has improved estimation accuracy. Moreover, it allows developing of new methods for low power design. The gate driving way can be easy calculated using logic simulations, but it is time-consuming method. So, the authors propose efficient and fast calculation procedures. The versatile algorithm for any circuit has been developed as well as very fast one for two-level circuits only. Results of new algorithms using were compared for a set of MCNC benchmark circuits.

Temperature sensors placement strategy for fault diagnosis in integrated circuits

In this paper, we present a new temperature sensor placement strategy. This placement method is proposed for fault diagnosis in integrated circuits (ICs). Simulation results of the new concept sensor placement strategy are presented. Statistical analyses of the yield of this testing method are shown.

Predictive Frequency Control For Low Power Digital Systems

The paper presents techniques of dynamic control of digital integrated systems performance considering die temperature. The dynamic clock throttling (DCT) and the dynamic frequency scaling (DFS) are taken into account. Allowing for the power-time product (pt) a new predictive method that improves the efficiency of DCT and DFS techniques is introduced

Thermal Placement in Hybrid Circuits—A Heuristic Approach

This paper deals with the placement of heat dissipating components in hybrid circuits. An optimum placement is found when the extreme temperatures on the substrate are minimized. Whereas classical techniques such as the gradient method require large computational efforts, a simple and very rapid heuristic method is presented here. The heuristic approach offers the advantage that it can be easily inserted in the design phase of the circuit.

Effective Supervisors for Predictive Methods of Dynamic Power Management

The paper presents new supervisors dedicated to predictive methods of dynamic power management, i.e. DCT (dynamic clock throttling), DFS (dynamic frequency scaling), and DVS (dynamic voltage scaling). The presented supervisors make decisions on the basis of current chip temperature; future, current and previous power dissipations. They consist in cooperation with operating system and they are dedicated to high efficiency systems. The proposed supervisors can be implemented in both software and hardware, e.g. as neural network. Not only performance gain but also energy profit can be made in systems that use these supervisors. Simulations results of considered cases show that theoretical improvement of the ideal supervisor is in the range of 7.38 to 16.17% for performance and of 2.47 to 9.88% for energy. The profit of the real supervise method depends on the complexity of supervisor.

Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation

Accurate analysis of CMOS gate power dissipation shows that amount of consumed energy depends on a reason of the gate switching. Number of activated inputs and type of applied signals have an influence on dynamic power dissipation of the gate due to dynamic reconfiguration of internal gate parasitic capacitors. Therefore, authors propose new modeling of dynamic power dissipation in static CMOS gates. Accurate modeling of dynamic power dissipation needs to take into consideration changes of all input signals. So, authors introduce new measure of digital circuit activity - gate driving way - for precise modeling of power dissipation. Based on conclusions flowing from the model analysis, authors propose method for two-level low-power circuits design.

Designing of low-power data oriented adders

Abstract The paper presents an idea of designing of low-power adders addressed to specific data processing. Mainly, the idea consists in proper choosing of 1-bit full adder cells for given probability of summed data, to obtain reduction in consumed power. Additionally different structures of the cells can be used, in one design, if it leads to reduction of power dissipation. To proper choice of structures of 1-bit full adders theirs energy characteristic versus summed data is needed. So, at the beginning we present results of assessment of a few 1-bit adder cells selected from literature and designed in UMC180 CMOS technology. The extended model of power consumption, taking into consideration input vector changes, was used, giving more accurate values than traditional model based on switching activity only. Thanks to the use of this model, obtained results allow detailed analysis of 1-bit adders on account of the using them in designing of low-power multi-bit adders summing specific data. Based on the results of analyses and given characteristic of summed data, appropriate full adder cells can be chosen to the final design of low-power data oriented adder. In specific case, cells which are made in different techniques can be used in multi-bit adder. A few examples are shown at the end of the paper.